Computer Architecture Set 18

Computer Science Engineering (CSE)

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This set of Computer Architecture Multiple Choice Questions & Answers (MCQs) focuses on Computer Architecture Set 18

Q1 | The method followed in case of node failure, wherein the node gets disabled is                     
Q2 | VLIW stands for?
Q3 | The main difference between the VLIW and the other approaches to improve performance is                         
Q4 | In VLIW the decision for the order of execution of the instructions depends on the program itself.
Q5 | The parallel execution of operations in VLIW is done according to the schedule determined by                       
Q6 | The VLIW processors are much simpler as they do not require of                     
Q7 | To compute the direction of the branch the VLIW uses                             
Q8 | EPIC stands for?
Q9 | The duration between the read and the mfc signal is               
Q10 | The minimum time delay between two successive memory read operations is               
Q11 |                       is the bottleneck, when it comes computer performance.
Q12 | The logical addresses generated by the cpu are mapped onto physical memory by                           
Q13 | VLSI stands for                         
Q14 | The cells in a row are connected to a common line called               
Q15 | The cells in each column are connected to               
Q16 | The word line is driven by the            
Q17 | A 16 X 8 Organisation of memory cells, can store upto            
Q18 | A memory organisation that can hold upto 1024 bits and has a minimum of 10 address lines can be organized into
Q19 | Circuits that can hold their state as long as power is applied is                 
Q20 | The number of external connections required in 16 X 8 memory organisation is            
Q21 | The advantage of CMOS SRAM over the transistor one’s is                     
Q22 | In a 4M-bit chip organisation has a total of 19 external connections.then it has                 address if 8 data lines are there.
Q23 | The Reason for the disregarding of the SRAM’s is                   
Q24 | The disadvantage of DRAM over SRAM is/are                 
Q25 | The reason for the cells to lose their state over time is                   
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