Computer Architecture Set 6

Computer Science Engineering (CSE)

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This set of Computer Architecture Multiple Choice Questions & Answers (MCQs) focuses on Computer Architecture Set 6

Q1 | The method which offers higher speeds of I/O transfers is                         
  • interrupts
  • memory mapping
  • program-controlled i/o
  • dma
Answer: dma
Explaination:
in dma the i/o devices are directly allowed to interact with the memory without the intervention of the processor and the transfers take place in the form of blocks increasing the speed of operation.
Q2 | The signal sent to the device from the processor to the device after receiving an interrupt is                         
  • interrupt-acknowledge
  • return signal
  • service signal
  • permission signal
Answer: interrupt-acknowledge
Explaination:
the processor upon receiving the interrupt should let the device know that its request is received.
Q3 | The time between the receiver of an interrupt and its service is               
  • interrupt delay
  • interrupt latency
  • cycle time
  • switching time
Answer: interrupt latency
Explaination:
the delay in servicing of an interrupt happens due to the time is taken for contact switch to take place.
Q4 | A single Interrupt line can be used to service n different devices.
  • true
  • false
Answer: true
Explaination:
none.
Q5 | The resistor which is attached to the service line is called            
  • push-down resistor
  • pull-up resistor
  • break down resistor
  • line resistor
Answer: pull-up resistor
Explaination:
this resistor is used to pull up the voltage of the interrupt service line.
Q6 | An interrupt that can be temporarily ignored is                         
  • vectored interrupt
  • non-maskable interrupt
  • maskable interrupt
  • high priority interrupt
Answer: maskable interrupt
Explaination:
the maskable interrupts are usually low priority interrupts which can be ignored if a higher priority process is being executed.
Q7 | Which interrupt is unmaskable?
  • rst 5.5
  • rst 7.5
  • trap
  • both rst 5.5 and 7.5
Answer: trap
Explaination:
the trap is a non- maskable interrupt as it deals with the ongoing process in the processor. the trap is initiated by the process being executed due to lack of data required
Q8 | When dealing with multiple devices interrupts, which mechanism is easy to implement?
  • polling method
  • vectored interrupts
  • interrupt nesting
  • none of the mentioned
Answer: polling method
Explaination:
in this method, the processor checks the irq bits of all the devices, whichever is enabled first that device is serviced.
Q9 | The interrupt servicing mechanism in which the requesting device identifies itself to the processor to be serviced is
  • polling
  • vectored interrupts
  • interrupt nesting
  • simultaneous requesting
Answer: vectored interrupts
Explaination:
none.
Q10 | In vectored interrupts, how does the device identify itself to the processor?
  • by sending its device id
  • by sending the machine code for the interrupt service routine
  • by sending the starting address of the service routine
  • none of the mentioned
Answer: by sending the starting address of the service routine
Explaination:
by sending the starting address of the routine the device ids the routine required and thereby identifying itself.
Q11 | The code sent by the device in vectored interrupt is            long.
  • upto 16 bits
  • upto 32 bits
  • upto 24 bits
  • 4-8 bits
Answer: 4-8 bits
Explaination:
none.
Q12 | The starting address sent by the device in vectored interrupt is called as
  • location id
  • interrupt vector
  • service location
  • service id
Answer: interrupt vector
Explaination:
none.
Q13 | The processor indicates to the devices that it is ready to receive interrupts
  • by enabling the interrupt request line
  • by enabling the irq bits
  • by activating the interrupt acknowledge line
  • none of the mentioned
Answer: by activating the interrupt acknowledge line
Explaination:
when the processor activates the acknowledge line the devices send their interrupts to the processor.
Q14 | Which table handle stores the addresses of the interrupt handling sub- routines?
  • interrupt-vector table
  • vector table
  • symbol link table
  • none of the mentioned
Answer: interrupt-vector table
Explaination:
none.
Q15 |                     method is used to establish priority by serially connecting all devices that request an interrupt.
  • vectored-interrupting
  • daisy chain
  • priority
  • polling
Answer: daisy chain
Explaination:
in the daisy chain mechanism, all the devices are connected using a single request line and they’re serviced based on the interrupting device’s priority.
Q16 | In daisy chaining device 0 will pass the signal only if it has                 
  • interrupt request
  • no interrupt request
  • both no interrupt and interrupt request
  • none of the mentioned
Answer: no interrupt request
Explaination:
in daisy chaining since there is only one request line and only one acknowledges line, the acknowledge signal passes from device to device until the one with the interrupt is found.
Q17 |               interrupt method uses register whose bits are set separately by interrupt signal for each device.
  • parallel priority interrupt
  • serial priority interrupt
  • daisy chaining
  • none of the mentioned
Answer: parallel priority interrupt
Explaination:
none.
Q18 |                               register is used for the purpose of controlling the status of each interrupt request in parallel priority interrupt.
  • mass
  • mark
  • make
  • mask
Answer: mask
Explaination:
none.
Q19 | The added output of the bits of the interrupt register and the mask register is set as an input of                               
  • priority decoder
  • priority encoder
  • process id encoder
  • multiplexer
Answer: priority encoder
Explaination:
in a parallel priority
Q20 | Interrupts initiated by an instruction is called as                 
  • internal
  • external
  • hardware
  • software
Answer: external
Explaination:
none.
Q21 | If during the execution of an instruction an exception is raised then
  • the instruction is executed and the exception is handled
  • the instruction is halted and the exception is handled
  • the processor completes the execution and saves the data and then handle the exception
  • none of the mentioned
Answer: the instruction is halted and the exception is handled
Explaination:
since the interrupt was raised during the execution of the instruction, the instruction cannot be executed and the exception is served immediately.
Q22 |            is/are types of exceptions.
  • trap
  • interrupt
  • system calls
  • all of the mentioned
Answer: all of the mentioned
Explaination:
none.
Q23 | The program used to find out errors is called                       
  • debugger
  • compiler
  • assembler
  • scanner
Answer: debugger
Explaination:
debugger is a program used to detect and correct errors in the program.
Q24 | The two facilities provided by the debugger is                       
  • trace points
  • break points
  • compile
  • both trace and break points
Answer: both trace and break points
Explaination:
the debugger provides us with the two facilities to improve the checking of errors.
Q25 | In trace mode of operation is
  • the program is interrupted after each detection
  • the program will not be stopped and the errors are sorted out after the complete program is scanned
  • there is no effect on the program, i.e the program is executed without rectification of errors
  • the program is halted only at specific points
Answer: the program is interrupted after each detection
Explaination:
in trace mode, the program is checked line by line and if errors are detected then exceptions are raised right away.
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