Computer Architecture Set 7

Computer Science Engineering (CSE)

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This set of Computer Architecture Multiple Choice Questions & Answers (MCQs) focuses on Computer Architecture Set 7

Q1 | What are the different modes of operation of a computer?
  • user and system mode
  • user and supervisor mode
  • supervisor and trace mode
  • supervisor, user and trace mode
Answer: user and supervisor mode
Explaination:
the user programs are in the user mode and the system crucial programs are in the supervisor mode.
Q2 | The instructions which can be run only supervisor mode are?
  • non-privileged instructions
  • system instructions
  • privileged instructions
  • exception instructions
Answer: privileged instructions
Explaination:
these instructions are those which can are crucial for the system’s performance and hence cannot be adultered by user programs, so is run only in supervisor mode.
Q3 | How is a privilege exception dealt with?
  • the program is halted and the system switches into supervisor mode and restarts the program execution
  • the program is stopped and removed from the queue
  • the system switches the mode and starts the execution of a new process
  • the system switches mode and runs the debugger
Answer: the program is halted and the system switches into supervisor mode and restarts the program execution
Explaination:
none.
Q4 | The DMA differs from the interrupt mode by                       
  • the involvement of the processor for the operation
  • the method of accessing the i/o devices
  • the amount of data transfer possible
  • none of the mentioned
Answer: none of the mentioned
Explaination:
dma is an approach of performing data transfers in bulk between memory and the external device without the intervention of the processor.
Q5 | The DMA transfers are performed by a control circuit called as                       
  • device interface
  • dma controller
  • data controller
  • overlooker
Answer: dma controller
Explaination:
the controller performs the functions that would normally be carried out by the processor.
Q6 | In DMA transfers, the required signals and addresses are given by the
  • processor
  • device drivers
  • dma controllers
  • the program itself
Answer: dma controllers
Explaination:
the dma controller acts as a processor for dma transfers and overlooks the entire process.
Q7 | After the completion of the DMA transfer, the processor is notified by
  • acknowledge signal
  • interrupt signal
  • wmfc signal
  • none of the mentioned
Answer: interrupt signal
Explaination:
the controller raises an interrupt signal to notify the processor that the transfer was complete.
Q8 | When the R/W bit of the status register of the DMA controller is set to 1.
  • read operation is performed
  • write operation is performed
  • read & write operation is performed
  • none of the mentioned
Answer: read operation is performed
Explaination:
none.
Q9 | The controller is connected to the
  • processor bus
  • system bus
  • external bus
  • none of the mentioned
Answer: system bus
Explaination:
the controller is directly connected to the system bus to provide faster transfer of data.
Q10 | Can a single DMA controller perform operations on two different disks simultaneously?
  • true
  • false
Answer: true
Explaination:
the dma controller can perform operations on two different disks if the appropriate details are known.
Q11 | The technique whereby the DMA controller steals the access cycles of the processor to operate is called
  • fast conning
  • memory con
  • cycle stealing
  • memory stealing
Answer: cycle stealing
Explaination:
the controller takes over the processor’s access cycles and performs memory operations.
Q12 | The technique where the controller is given complete access to main memory is                       
  • cycle stealing
  • memory stealing
  • memory con
  • burst mode
Answer: burst mode
Explaination:
the controller is given full control of the memory access cycles and can transfer blocks at a faster rate.
Q13 | The controller uses            to help with the transfers when handling network interfaces.
  • input buffer storage
  • signal enhancers
  • bridge circuits
  • all of the mentioned
Answer: input buffer storage
Explaination:
the controller stores the data to transfer in the buffer and then transfers it.
Q14 | To overcome the conflict over the possession of the BUS we use               
  • optimizers
  • bus arbitrators
  • multiple bus structure
  • none of the mentioned
Answer: bus arbitrators
Explaination:
the bus arbitrator is used to overcome the contention over the bus possession.
Q15 | The registers of the controller are
  • 64 bits
  • 24 bits
  • 32 bits
  • 16 bits
Answer: 32 bits
Explaination:
none.
Q16 | When the process requests for a DMA transfer?
  • then the process is temporarily suspended
  • the process continues execution
  • another process gets executed
  • process is temporarily suspended & another process gets executed
Answer: process is temporarily suspended & another process gets executed
Explaination:
the process requesting the transfer is paused and the operation is performed, meanwhile another process is run on the processor.
Q17 | The DMA transfer is initiated by
  • processor
  • the process being executed
  • i/o devices
  • os
Answer: i/o devices
Explaination:
the transfer can only be initiated by an instruction of a program being executed.
Q18 | To resolve the clash over the access of the system BUS we use               
  • multiple bus
  • bus arbitrator
  • priority access
  • none of the mentioned
Answer: bus arbitrator
Explaination:
the bus arbitrator is used to allow a device to access the bus based on certain parameters.
Q19 | The device which is allowed to initiate data transfers on the BUS at any time is called            
  • bus master
  • processor
  • bus arbitrator
  • controller
Answer: bus master
Explaination:
the device which is currently accessing the bus is called as the bus master.
Q20 |               BUS arbitration approach uses the involvement of the processor.
  • centralised arbitration
  • distributed arbitration
  • random arbitration
  • all of the mentioned
Answer: centralised arbitration
Explaination:
in this approach, the processor takes into account the various parameters and assigns the bus to that device.
Q21 | The circuit used for the request line is a                     
  • open-collector
  • ex-or circuit
  • open-drain
  • nand circuit
Answer: open-drain
Explaination:
none.
Q22 | The Centralised BUS arbitration is
  • acknowledge signal
  • bus grant signal
  • response signal
  • none of the mentioned
Answer: bus grant signal
Explaination:
the grant signal is passed from one device to the other until the device that has requested is found.
Q23 | Once the BUS is granted to a device
  • it activates the bus busy line
  • performs the required operation
  • raises an interrupt
  • all of the mentioned
Answer: it activates the bus busy line
Explaination:
the bus busy activated indicates that the bus is already allocated to a device and is being used.
Q24 | When the processor receives the request from a device, it responds by sending            
  • open-drain circuit
  • open-collector circuit
  • ex-or circuit
  • nor circuit
Answer: open-collector circuit
Explaination:
none.
Q25 | After the device completes its operation            assumes the control of the BUS.
  • another device
  • processor
  • controller
  • none of the mentioned
Answer: processor
Explaination:
after the device completes the operation it releases the bus and the processor takes over it.
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