Computer Architecture Set 10

Computer Science Engineering (CSE)

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This set of Computer Architecture Multiple Choice Questions & Answers (MCQs) focuses on Computer Architecture Set 10

Q1 | The double buffer is used for
  • enabling retrieval of multiple bits of input
  • combining the input and output operations
  • extending the buffer capacity
  • none of the mentioned
Answer: enabling retrieval of multiple bits of input
Explaination:
none.
Q2 | UART stands for                   
  • universal asynchronous relay transmission
  • universal accumulator register transfer
  • universal asynchronous receiver transmitter
  • none of the mentioned
Answer: universal asynchronous receiver transmitter
Explaination:
the uart is a standard developed for designing serial ports.
Q3 | The key feature of UART is                     
  • its architectural design
  • its simple implementation
  • its general purpose usage
  • its enhancement of connecting low speed devices
Answer: its enhancement of connecting low speed devices
Explaination:
none.
Q4 | The data transfer in UART is done in
  • asynchronous start stop format
  • synchronous start stop format
  • isochronous format
  • ebdic format
Answer: asynchronous start stop format
Explaination:
this basically means that the data transfer is done in asynchronous mode.
Q5 | The standard used in serial ports to facilitate communication is            
  • rs-246
  • rs-lnk
  • rs-232-c
  • both rs-246 and rs-lnk
Answer: rs-232-c
Explaination:
this is a standard that acts as a protocol for message communication involving serial ports.
Q6 | In a serial port interface, the INTR line is connected to            
  • status register
  • shift register
  • chip select
  • none of the mentioned
Answer: status register
Explaination:
none.
Q7 | The PCI follows a set of standards primarily used in            PC’s.
  • intel
  • motorola
  • ibm
  • sun
Answer: ibm
Explaination:
the pci bus has a closer resemblance to ibm architecture.
Q8 | The               is the BUS used in Macintosh PC’s.
  • nubus
  • eisa
  • pci
  • none of the mentioned
Answer: nubus
Explaination:
the nubus is an extension of the processor bus in macintosh pc’s.
Q9 | The key feature of the PCI BUS is
  • low cost connectivity
  • plug and play capability
  • expansion of bandwidth
  • none of the mentioned
Answer: plug and play capability
Explaination:
the pci bus was the first to introduce plug and play interface for i/o devices.
Q10 | PCI stands for                 
  • peripheral component interconnect
  • peripheral computer internet
  • processor computer interconnect
  • processor cable interconnect
Answer: peripheral component interconnect
Explaination:
the pci bus is used as an extension for the processor bus.
Q11 | The PCI BUS supports            address space/s.
  • i/o
  • memory
  • configuration
  • all of the mentioned
Answer: all of the mentioned
Explaination:
the pci bus is mainly built to provide a wide range of connectivity for devices.
Q12 |               address space gives the PCI its plug and plays capability.
  • configuration
  • i/o
  • memory
  • all of the mentioned
Answer: configuration
Explaination:
the configuration address space is used to store the details of the connected device.
Q13 |            provides a separate physical connection to the memory.
  • pci bus
  • pci interface
  • pci bridge
  • switch circuit
Answer: pci bridge
Explaination:
the pci bridge is a circuit that acts as a bridge between the bus and the memory.
Q14 | When transferring data over the PCI BUS, the master as to hold the address until the completion of the transfer to the slave.
  • true
  • false
Answer: false
Explaination:
the address is stored by the slave in a buffer and hence it is not required by the master to hold it.
Q15 | The master is also called as            in PCI terminology.
  • initiator
  • commander
  • chief
  • starter
Answer: initiator
Explaination:
the master is also called as an initiator in pci terminology as it is the one that initiates a data transfer.
Q16 | Signals whose names end in          are asserted in the low voltage state.
  • $
  • #
  • *
  • !
Answer: #
Explaination:
none.
Q17 | A complete transfer operation over the BUS, involving the address and a burst of data is called            
  • transaction
  • transfer
  • move
  • procedure
Answer: transaction
Explaination:
none.
Q18 | The device connected to the BUS are given addresses of          bit.
  • 24
  • 64
  • 32
  • 16
Answer: 64
Explaination:
each of the devices connected to the bus will be allocated an address during the initialization phase.
Q19 | The PCI BUS has            interrupt request lines.
  • 6
  • 1
  • 4
  • 3
Answer: 4
Explaination:
the interrupt request lines are used by the devices connected to raise the interrupts.
Q20 |            signal is sent by the initiator to indicate the duration of the transaction.
  • frame#
  • irdy#
  • tmy#
  • seld#
Answer: frame#
Explaination:
the frame signal is used
Q21 |               signal is used to enable commands.
  • frame#
  • irdy#
  • tmy#
  • c/be#
Answer: c/be#
Explaination:
the signal is used to enable 4 command lines.
Q22 | IRDY# signal is used for                 
  • selecting the interrupt line
  • sending an interrupt
  • saying that the initiator is ready
  • none of the mentioned
Answer: saying that the initiator is ready
Explaination:
the initiator transmits this signal to tell the target that it is ready.
Q23 | The signal used to indicate that the slave is ready is            
  • slry#
  • trdy#
  • dsdy#
  • none of the mentioned
Answer: trdy#
Explaination:
none.
Q24 | DEVSEL# signal is used                     
  • to select the device
  • to list all the devices connected
  • by the device to indicate that it is ready for a transaction
  • none of the mentioned
Answer: by the device to indicate that it is ready for a transaction
Explaination:
this is signal is activated by the device after it as recognized the address and commands put on the bus.
Q25 | The signal used to initiate device select                   
  • irdy#
  • s/be
  • devsel#
  • idsel#
Answer: idsel#
Explaination:
this signal is used to initialization of device select.
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