Computer Architecture Set 22

Computer Science Engineering (CSE)

Practice Mode Previous Next
On This Page

This set of Computer Architecture Multiple Choice Questions & Answers (MCQs) focuses on Computer Architecture Set 22

Q1 | The technique of searching for a block by going through all the tags is
  • linear search
  • binary search
  • associative search
  • none of the mentioned
Answer: associative search
Explaination:
none.
Q2 | The set-associative map technique is a combination of the direct and associative technique.
  • true
  • false
Answer: true
Explaination:
the combination of the efficiency of the associative method and the cheapness of the direct mapping, we get the set-associative mapping.
Q3 | In set-associative technique, the blocks are grouped into               sets.
  • 4
  • 8
  • 12
  • 6
Answer: 6
Explaination:
the set-associative technique groups the blocks into different sets.
Q4 | A control bit called                     has to be provided to each block in set- associative.
  • idol bit
  • valid bit
  • reference bit
  • all of the mentioned
Answer: valid bit
Explaination:
the valid bit is used to indicate that the block holds valid information.
Q5 | The bit used to indicate whether the block was recently used or not is
  • idol bit
  • control bit
  • reference bit
  • dirty bit
Answer: dirty bit
Explaination:
the dirty bit is used to show that the block was recently modified and for a replacement algorithm.
Q6 | Data which is not up-to date is called as                 
  • spoilt data
  • stale data
  • dirty data
  • none of the mentioned
Answer: stale data
Explaination:
none.
Q7 | The main memory is structured into modules each with its own address register called               
  • abr
  • tlb
  • pc
  • ir
Answer: abr
Explaination:
abr stands for address buffer register.
Q8 | When consecutive memory locations are accessed only one module is accessed at a time.
  • true
  • false
Answer: true
Explaination:
in a modular approach to memory structuring only one module can be accessed at a time.
Q9 | In memory interleaving, the lower order bits of the address is used to
  • get the data
  • get the address of the module
  • get the address of the data within the module
  • none of the mentioned
Answer: get the address of the module
Explaination:
to implement parallelism in data access we use interleaving.
Q10 | The number successful accesses to memory stated as a fraction is called as
  • hit rate
  • miss rate
  • success rate
  • access rate
Answer: hit rate
Explaination:
the hit rate is an important factor in performance measurement.
Q11 | The number failed attempts to access memory, stated in the form of a fraction is called as                     
  • hit rate
  • miss rate
  • failure rate
  • delay rate
Answer: miss rate
Explaination:
the miss rate is a key factor in deciding the type of replacement algorithm.
Q12 | In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one, when            occurs.
  • delay
  • miss
  • hit
  • delayed hit
Answer: miss
Explaination:
miss usually occurs when the memory block required is not present in the cache.
Q13 | In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are incremented by one and others remain same, in the case of
  • hit
  • miss
  • delay
  • none of the mentioned
Answer: hit
Explaination:
if the referenced block is present in the memory it is called as hit.
Q14 | If hit rates are well below 0.9, then they’re called as speedy computers.
  • true
  • false
Answer: false
Explaination:
it has to be above 0.9 for speedy computers.
Q15 | The extra time needed to bring the data into memory in case of a miss is called as                       
  • delay
  • propagation time
  • miss penalty
  • none of the mentioned
Answer: miss penalty
Explaination:
none.
Q16 | The miss penalty can be reduced by improving the mechanisms for data transfer between the different levels of hierarchy.
  • true
  • false
Answer: true
Explaination:
the extra time needed to bring the data into memory in case of a miss is called as miss penalty.
Q17 | The CPU is also called as                   
  • processor hub
  • isp
  • controller
  • all of the mentioned
Answer: isp
Explaination:
isp stands for instruction set processor.
Q18 | A common strategy for performance is making various functional units operate parallelly.
  • true
  • false
Answer: true
Explaination:
by parallelly accessing data we can have a pipelined processor.
Q19 | The PC gets incremented
  • after the instruction decoding
  • after the ir instruction gets executed
  • after the fetch cycle
  • none of the mentioned
Answer: after the fetch cycle
Explaination:
the pc always points to the next instruction to be executed.
Q20 | Which register in the processor is single directional?
  • mar
  • mdr
  • pc
  • temp
Answer: mar
Explaination:
the mar is single directional as it just takes the address from the processor bus and passes it to the external bus.
Q21 | The transparent register/s is/are
  • y
  • z
  • temp
  • all of the mentioned
Answer: all of the mentioned
Explaination:
these registers are usually used to store temporary values.
Q22 | Which register is connected to the MUX?
  • y
  • z
  • r0
  • temp
Answer: y
Explaination:
the mux can either read the operand from the y register or increment the pc.
Q23 | The registers, ALU and the interconnecting path together are called as               
  • control path
  • flow path
  • data path
  • none of the mentioned
Answer: data path
Explaination:
none.
Q24 | The input and output of the registers are governed by                       
  • transistors
  • diodes
  • gates
  • switches
Answer: switches
Explaination:
none.
Q25 | When two or more clock cycles are used to complete data transfer it is called as                   
  • single phase clocking
  • multi-phase clocking
  • edge triggered clocking
  • none of the mentioned
Answer: multi-phase clocking
Explaination:
this is basically used in systems without edge-triggered flip flops.
Previous Next