Computer Architecture Set 2

Computer Science Engineering (CSE)

Practice Mode Previous Next
On This Page

This set of Computer Architecture Multiple Choice Questions & Answers (MCQs) focuses on Computer Architecture Set 2

Q1 |               are used to overcome the difference in data transfer speeds of various devices.
  • speed enhancing circuitory
  • bridge circuits
  • multiple buses
  • buffer registers
Answer: buffer registers
Explaination:
by using buffer registers, the processor sends the data to the i/o device at the processor speed and the data gets stored in the buffer. after that the data gets sent to or from the buffer to the devices at the device speed.
Q2 | To extend the connectivity of the processor bus we use                   
  • pci bus
  • scsi bus
  • controllers
  • multiple bus
Answer: pci bus
Explaination:
pci bus is used to connect other peripheral devices that require a direct connection with the processor.
Q3 | IBM developed a bus standard for their line of computers ‘PC AT’ called
  • ib bus
  • m-bus
  • isa
  • none of the mentioned
Answer: isa
Explaination:
none.
Q4 | The bus used to connect the monitor to the CPU is               
  • pci bus
  • scsi bus
  • memory bus
  • rambus
Answer: scsi bus
Explaination:
scsi bus is usually used to connect video devices to the processor.
Q5 | ANSI stands for                       
  • american national standards institute
  • american national standard interface
  • american network standard interfacing
  • american network security interrupt
Answer: american national standards institute
Explaination:
none.
Q6 |            register Connected to the Processor bus is a single-way transfer capable.
  • pc
  • ir
  • temp
  • z
Answer: z
Explaination:
the z register is a special register which can interact with the processor bus only.
Q7 | In multiple Bus organisation, the registers are collectively placed and referred as               
  • set registers
  • register file
  • register block
  • map registers
Answer: register file
Explaination:
none.
Q8 | The main advantage of multiple bus organisation over a single bus is            
  • reduction in the number of cycles for execution
  • increase in size of the registers
  • better connectivity
  • none of the mentioned
Answer: reduction in the number of cycles for execution
Explaination:
none.
Q9 | The ISA standard Buses are used to connect                         
  • ram and processor
  • gpu and processor
  • harddisk and processor
  • cd/dvd drives and processor
Answer: harddisk and processor
Explaination:
none.
Q10 | During the execution of the instructions, a copy of the instructions is placed in the               
  • register
  • ram
  • system heap
  • cache
Answer: cache
Explaination:
none.
Q11 | Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster?
  • a
  • b
  • both take the same time
  • insufficient information
Answer: a
Explaination:
the performance of a system can be found out using the basic performance formula.
Q12 | A processor performing fetch or decoding of different instruction during the execution of another instruction is called               
  • super-scaling
  • pipe-lining
  • parallel computation
  • none of the mentioned
Answer: pipe-lining
Explaination:
pipe-lining is the process of improving the performance of the system by processing different instructions at the same time, with only one instruction performing one specific operation.
Q13 | The clock rate of the processor can be improved by                     
  • improving the ic technology of the logic circuits
  • reducing the amount of processing done in one step
  • by using the overclocking method
  • all of the mentioned
Answer: all of the mentioned
Explaination:
the clock rate(frequency of the processor) is the hardware dependent quantity it is fixed for a given processor.
Q14 | An optimizing Compiler does
  • better compilation of the given piece of code
  • takes advantage of the type of processor and reduces its process time
  • does better memory management
  • none of the mentioned
Answer: takes advantage of the type of processor and reduces its process time
Explaination:
an optimizing compiler is a compiler designed for the specific purpose of increasing the operation speed of the processor by reducing the time taken to compile the program instructions.
Q15 | SPEC stands for                                  
  • standard performance evaluation code
  • system processing enhancing code
  • system performance evaluation corporation
  • standard processing enhancement corporation
Answer: system performance evaluation corporation
Explaination:
spec is a corporation that started to standardize the evaluation method of a system’s performance.
Q16 | As of 2000, the reference system to find the performance of a system is
  • ultra sparc 10
  • sun sparc
  • sun ii
  • none of the mentioned
Answer: ultra sparc 10
Explaination:
in spec system of measuring a system’s performance, a system is used as a reference against which other systems are compared and performance is determined.
Q17 | If a processor clock is rated as 1250 million cycles per second, then its clock period is                   
  • 1.9 * 10-10 sec
  • 1.6 * 10-9 sec
  • 1.25 * 10-10 sec
  • 8 * 10-10 sec
Answer: 8 * 10-10 sec
Explaination:
none.
Q18 | If the instruction, Add R1, R2, R3 is executed in a system that is pipe-lined, then the value of S is (Where S is a term of the Basic performance equation)?
  • 3
  • ~2
  • ~1
  • 6
Answer: ~1
Explaination:
s is the number of steps
Q19 | CISC stands for                 
  • complete instruction sequential compilation
  • computer integrated sequential compiler
  • complex instruction set computer
  • complex instruction sequential compilation
Answer: complex instruction set computer
Explaination:
cisc is a type of system architecture where complex instructions
Q20 | In the case of, Zero-address instruction method the operands are stored in            
  • registers
  • accumulators
  • push down stack
  • cache
Answer: push down stack
Explaination:
in this case, the operands are implicitly loaded onto the alu.
Q21 | As of 2000, the reference system to find the SPEC rating are built with             Processor.
  • intel atom sparc 300mhz
  • ultra sparc -iii 300mhz
  • amd neutrino series
  • asus a series 450 mhz
Answer: ultra sparc -iii 300mhz
Explaination:
none.
Q22 | The instruction, Add #45,R1 does
  • adds the value of 45 to the address of r1 and stores 45 in that address
  • adds 45 to the value of r1 and stores it in r1
  • finds the memory location 45 and adds that content to that of r1
  • none of the mentioned
Answer: adds 45 to the value of r1 and stores it in r1
Explaination:
the instruction is using immediate addressing mode hence the value is stored in the location 45 is added.
Q23 | The addressing mode which makes use of in-direction pointers is               
  • indirect addressing mode
  • index addressing mode
  • relative addressing mode
  • offset addressing mode
Answer: indirect addressing mode
Explaination:
in this addressing mode, the value of the register serves as another memory location and hence we use pointers to get the data.
Q24 | In the following indexed addressing mode instruction, MOV 5(R1), LOC the effective address is               
  • ea = 5+r1
  • ea = r1
  • ea = [r1]
  • ea = 5+[r1]
Answer: ea = 5+[r1]
Explaination:
this instruction is in base with offset addressing mode.
Q25 | The addressing mode/s, which uses the PC instead of a general purpose register is               
  • indexed with offset
  • relative
  • direct
  • both indexed with offset and direct
Answer: relative
Explaination:
in this, the contents of the pc are directly incremented.
Previous Next