Computer Architecture Set 8

Computer Science Engineering (CSE)

Practice Mode Previous Next
On This Page

This set of Computer Architecture Multiple Choice Questions & Answers (MCQs) focuses on Computer Architecture Set 8

Q1 | The BUS busy line is used
  • to indicate the processor is busy
  • to indicate that the bus master is busy
  • to indicate the bus is already allocated
  • none of the mentioned
Answer: to indicate the bus is already allocated
Explaination:
none.
Q2 | If two devices A and B contesting for the BUS have ID’s 5 and 6 respectively, which device gets the BUS based on the Distributed arbitration.
  • device a
  • device b
  • insufficient information
  • none of the mentioned
Answer: device b
Explaination:
the device id’s of both the devices are passed on the lines and since the value of b is greater after the or operation it gets the bus.
Q3 | In Distributed arbitration, the device requesting the BUS               
  • asserts the start arbitration signal
  • sends an interrupt signal
  • sends an acknowledge signal
  • none of the mentioned
Answer: asserts the start arbitration signal
Explaination:
none.
Q4 | How is a device selected in Distributed arbitration?
  • to connect the various devices to the cpu
  • to provide a path for communication between the processor and other devices
  • to facilitate data transfer between various devices
  • all of the mentioned
Answer: to connect the various devices to the cpu
Explaination:
the bus is used to allow the passage of commands and data between cpu and devices.
Q5 | The device which starts data transfer is called                       
  • master
  • transactor
  • distributor
  • initiator
Answer: initiator
Explaination:
the device which starts the data transfer is called an initiator.
Q6 | The device which interacts with the initiator is                       
  • slave
  • master
  • responder
  • friend
Answer: slave
Explaination:
the device which receives the commands from the initiator for data transfer.
Q7 | In synchronous BUS, the devices get the timing signals from                       
  • timing generator in the device
  • a common clock line
  • timing signals are not used at all
  • none of the mentioned
Answer: a common clock line
Explaination:
the devices receive their timing signals from the clock line of the bus.
Q8 | The delays caused in the switching of the timing signals is due to                       
  • memory access time
  • wmfc
  • propagation delay
  • processor delay
Answer: propagation delay
Explaination:
the time taken for the signal to reach the bus from the device or the circuit accounts for this delay.
Q9 | The time for which the data is to be on the BUS is affected by                       
  • propagation delay of the circuit
  • setup time of the device
  • memory access time
  • propagation delay of the circuit & setup time of the device
Answer: propagation delay of the circuit & setup time of the device
Explaination:
the time for which the data is held is larger than the time taken for propagation delay and setup time.
Q10 | The Master strobes the slave at the end of each clock cycle in Synchronous BUS.
  • true
  • false
Answer: true
Explaination:
none.
Q11 | Which is fed into the BUS first by the initiator?
  • data
  • address
  • commands or controls
  • address, commands or controls
Answer: address, commands or controls
Explaination:
none.
Q12 | The devices with variable speeds are usually connected using asynchronous BUS.
  • true
  • false
Answer: true
Explaination:
the devices with variable speeds are connected using asynchronous bus, as the devices share a master-slave relationship.
Q13 | The MSYN signal is initiated
  • soon after the address and commands are loaded
  • soon after the decoding of the address
  • after the slave gets the commands
  • none of the mentioned
Answer: soon after the decoding of the address
Explaination:
this signal is activated by the master to tell the slave that the required commands are on the bus.
Q14 | In IBM’s S360/370 systems            lines are used to select the I/O devices.
  • scan in and out
  • connect
  • search
  • peripheral
Answer: scan in and out
Explaination:
the signal is used to scan and connect to input or output devices.
Q15 | The meter in and out lines are used for                       
  • monitoring the usage of devices
  • monitoring the amount of data transferred
  • measure the cpu usage
  • none of the mentioned
Answer: monitoring the usage of devices
Explaination:
the line is used to monitor the usage of the device for a process.
Q16 | MRDC stands for                 
  • memory read enable
  • memory ready command
  • memory re-direct command
  • none of the mentioned
Answer: memory ready command
Explaination:
the command is used to initiate a read from memory operation.
Q17 | The BUS that allows I/O, memory and Processor to coexist is                 
  • attributed bus
  • processor bus
  • backplane bus
  • external bus
Answer: backplane bus
Explaination:
none.
Q18 | The transmission on the asynchronous BUS is also called            
  • switch mode transmission
  • variable transfer
  • bulk transfer
  • hand-shake transmission
Answer: hand-shake transmission
Explaination:
the asynchronous transmission is termed as hand-shake transfer because the master intimates the slave after each step of the transfer.
Q19 | Asynchronous mode of transmission is suitable for systems with multiple peripheral devices.
  • true
  • false
Answer: true
Explaination:
this mode of transmission is suitable for multiple device situation as it supports variable speed transfer.
Q20 | The asynchronous BUS mode of transmission allows for a faster mode of data transfer.
  • true
  • false
Answer: false
Explaination:
none.
Q21 |               serves as an intermediary between the device and the BUSes.
  • interface circuits
  • device drivers
  • buffers
  • none of the mentioned
Answer: interface circuits
Explaination:
the interface circuits act as a hardware interface between the device and the software side.
Q22 | The side of the interface circuits, that has the data path and the control signals to transfer data between interface and device is            
  • bus side
  • port side
  • hardwell side
  • software side
Answer: port side
Explaination:
this side connects the device to the motherboard.
Q23 | What is the interface circuit?
  • helps in installing of the software driver for the device
  • houses the buffer that helps in data transfer
  • helps in the decoding of the address on the address bus
  • none of the mentioned
Answer: helps in the decoding of the address on the address bus
Explaination:
once the address is put on the bus the interface circuit decodes the address and uses the buffer space to transfer data.
Q24 | The conversion from parallel to serial data transmission and vice versa takes place inside the interface circuits.
  • true
  • false
Answer: true
Explaination:
by doing this the interface circuits provide a better interconnection between devices.
Q25 | The Interface circuits generate the appropriate timing signals required by the BUS control scheme.
  • true
  • false
Answer: true
Explaination:
the interface circuits generate the required clock signal for the synchronous mode of transfer.
Previous Next