Computer Architecture Set 16 MCQs

Q1 | The banked registers are used for

switching between supervisor and interrupt mode
extended storing
same as other general purpose registers
none of the mentioned

Answer: switching between supervisor and interrupt mode

Explaination:
when switching from one mode to another, instead of storing the register contents somewhere else it’ll be kept in the duplicate registers and the new values are stored in the actual registers.

Q2 | Each instruction in ARM machines is encoded into Word.

2 byte
3 byte
4 byte
8 byte

Answer: 4 byte

Explaination:
the data is encrypted to make them secure.

Q3 | All instructions in ARM are conditionally executed.

true
false

Answer: true

Explaination:
none.

Q4 | The addressing mode where the EA of the operand is the contents of Rn is

pre-indexed mode
pre-indexed with write back mode
post-indexed mode
none of the mentioned

Answer: post-indexed mode

Explaination:
none.

Q5 | The effective address of the instruction written in Post-indexed mode, MOVE[Rn]+Rm is

ea = [rn]
ea = [rn + rm]
ea = [rn] + rm
ea = [rm] + rn

Answer: ea = [rn]

Explaination:
effective address is the address that the computer acquires from the current instruction being executed.

Q6 | symbol is used to signify write back mode.

#
^
&
!

Answer: !

Explaination:
none.

Q7 | The instruction, MLA R0,R1,R2,R3 performs

r0<-[r1]+[r2]+[r3]
r3<-[r0]+[r1]+[r2]
r0<-[r1]*[r2]+[r3]
r3<-[r0]*[r1]+[r2]

Answer: r0<-[r1]*[r2]+[r3]

Explaination:
the mla instruction is used perform addition and multiplication together.

Q8 | instruction is used to get the 1’s complement of the operand.

comp
bic
~cmp
mvn

Answer: mvn

Explaination:
the complement of all the bits of a data is its 1’s compliment.

Q9 | The offset used in the conditional branching is bit.

24
32
16
8

Answer: 24

Explaination:
the offset is used to get the new branching address of the process.

Q10 | The condition to check whether the branch should happen or not is given by

the lower order 8 bits of the instruction
the higher order 4 bits of the instruction
the lower order 4 bits of the instruction
the higher order 8 bits of the instruction

Answer: the higher order 4 bits of the instruction

Explaination:
none.

Q11 | directive is used to indicate the beginning of the program instruction or data.

equ
start
area
space

Answer: area

Explaination:
none.

Q12 | directive specifies the start of the execution.

start
entry
main
origin

Answer: entry

Explaination:
this directive indicates the beginning of the executable part of the program.

Q13 | directives are used to initialize operands.

int
dataword
reserve
dcd

Answer: dcd

Explaination:
these directives are used to initialize the operands to a user defined value or a default value.

Q14 | directive is used to name the register used for execution of an instruction.

assign
rn
name
declare

Answer: rn

Explaination:
this instruction is used to list the registers used for execution.

Q15 | The pseudo instruction used to load an address into the register is

load
adr
assign
psload

Answer: adr

Explaination:
none.

Q16 | The size of the floating registers can be extended upto

128 bit
256 bit
80 bit
64 bit

Answer: 80 bit

Explaination:
none.

Q17 | The floating point numbers are stored in general purpose register in IA-32.

true
false

Answer: false

Explaination:
the floating registers are not stored in general purpose registers as they have a real part and a decimal part.

Q18 | The PC is incorporated with the help of general purpose registers.

true
false

Answer: false

Explaination:
registers are not used to incorporate pc as in other architectures, but a separate space is allocated to it.

Q19 | IOPL stands for

input/output privilege level
input output process link
internal output process link
internal offset privilege level

Answer: input/output privilege level

Explaination:
this indicates the security

Q20 | In IA-32 architecture along with the general flags, the other conditional flags provided are

iopl
if
tf
all of the mentioned

Answer: all of the mentioned

Explaination:
these flags are basically used to check the system for exceptions.

Q21 | The register used to serve as PC is called as

indirection register
instruction pointer
r-32
none of the mentioned

Answer: instruction pointer

Explaination:
the pc is used to store the next instruction that is going to be executed.

Q22 | The IA-32 processor can switch between 16 bit operation and 32 bit operation with the help of instruction prefix bit.

true
false

Answer: true

Explaination:
this switching enables a wide range of operations to be performed.

Q23 | The Bit extension of the register is denoted with the help of symbol.

$
`
e
~

Answer: e

Explaination:
this is used to extend the size of the register.

Q24 | The instruction, ADD R1, R2, R3 is decoded as

r1<-[r1]+[r2]+[r3]
r3<-[r1]+[r2]
r3<-[r1]+[r2]+[r3]
r1<-[r2]+[r3]

Answer: r1<-[r2]+[r3]

Explaination:
none.

Q25 | The instruction JG loop does

jumps to the memory location loop if the result of the most recent arithmetic op is even
jumps to the memory location loop if the result of the most recent arithmetic op is greater than 0
jumps to the memory location loop if the test condition is satisfied with the value of loop
none of the mentioned

Answer: jumps to the memory location loop if the result of the most recent arithmetic op is greater than 0

Explaination:
this instruction is used to cause a branch based on the outcome of the arithmetic operation.