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This set of Computer Architecture Multiple Choice Questions & Answers (MCQs) focuses on Computer Architecture Set 18

Q1 | The method followed in case of node failure, wherein the node gets disabled is                     
  • stonith
  • fibre channel
  • fencing
  • none of the mentioned
Q2 | VLIW stands for?
  • very long instruction word
  • very long instruction width
  • very large instruction word
  • very long instruction width
Q3 | The main difference between the VLIW and the other approaches to improve performance is                         
  • cost effectiveness
  • increase in performance
  • lack of complex hardware design
  • all of the mentioned
Q4 | In VLIW the decision for the order of execution of the instructions depends on the program itself.
  • true
  • false
Q5 | The parallel execution of operations in VLIW is done according to the schedule determined by                       
  • task scheduler
  • interpreter
  • compiler
  • encoder
Q6 | The VLIW processors are much simpler as they do not require of                     
  • computational register
  • complex logic circuits
  • ssd slots
  • scheduling hardware
Q7 | To compute the direction of the branch the VLIW uses                             
  • seekers
  • heuristics
  • direction counter
  • compass
Q8 | EPIC stands for?
  • explicitly parallel instruction computing
  • external peripheral integrating component
  • external parallel instruction computing
  • none of the mentioned
Q9 | The duration between the read and the mfc signal is               
  • access time
  • latency
  • delay
  • cycle time
Q10 | The minimum time delay between two successive memory read operations is               
  • cycle time
  • latency
  • delay
  • none of the mentioned
Q11 |                       is the bottleneck, when it comes computer performance.
  • memory access time
  • memory cycle time
  • delay
  • latency
Q12 | The logical addresses generated by the cpu are mapped onto physical memory by                           
  • relocation register
  • tlb
  • mmu
  • none of the mentioned
Q13 | VLSI stands for                         
  • very large scale integration
  • very large stand-alone integration
  • volatile layer system interface
  • none of the mentioned
Q14 | The cells in a row are connected to a common line called               
  • work line
  • word line
  • length line
  • principle diagonal
Q15 | The cells in each column are connected to               
  • word line
  • data line
  • read line
  • sense/ write line
Q16 | The word line is driven by the            
  • chip select
  • address decoder
  • data line
  • control line
Q17 | A 16 X 8 Organisation of memory cells, can store upto            
  • 256 bits
  • 1024 bits
  • 512 bits
  • 128 bits
Q18 | A memory organisation that can hold upto 1024 bits and has a minimum of 10 address lines can be organized into
  • 128 x 8
  • 256 x 4
  • 512 x 2
  • 1024 x 1
Q19 | Circuits that can hold their state as long as power is applied is                 
  • dynamic memory
  • static memory
  • register
  • cache
Q20 | The number of external connections required in 16 X 8 memory organisation is            
  • 14
  • 19
  • 15
  • 12
Q21 | The advantage of CMOS SRAM over the transistor one’s is                     
  • low cost
  • high efficiency
  • high durability
  • low power consumption
Q22 | In a 4M-bit chip organisation has a total of 19 external connections.then it has                 address if 8 data lines are there.
  • 10
  • 8
  • 9
  • 12
Q23 | The Reason for the disregarding of the SRAM’s is                   
  • low efficiency
  • high power consumption
  • high cost
  • all of the mentioned
Q24 | The disadvantage of DRAM over SRAM is/are                 
  • lower data storage capacities
  • higher heat dissipation
  • the cells are not static
  • all of the mentioned
Q25 | The reason for the cells to lose their state over time is                   
  • the lower voltage levels
  • usage of capacitors to store the charge
  • use of shift registers
  • none of the mentioned