Computer Architecture Set 26

Computer Science Engineering (CSE)

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This set of Computer Architecture Multiple Choice Questions & Answers (MCQs) focuses on Computer Architecture Set 26

Q1 | The fetch and execution cycles are interleaved with the help of ________
  • Modification in processor architecture
  • Clock
  • Special unit
  • Control unit
Answer: Clock
Q2 | Each stage in pipelining should be completed within ____ cycle.
  • 1
  • 2
  • 3
  • 4
Answer: 1
Q3 | To increase the speed of memory access in pipelining, we make use of _______
  • Special memory locations
  • Special purpose registers
  • Cache
  • Buffers
Answer: Cache
Q4 | The situation wherein the data of operands are not available is called ______
  • Data hazard
  • Stock
  • Deadlock
  • Structural hazard
Answer: Data hazard
Q5 | The time lost due to the branch instruction is often referred to as _____
  • Latency
  • Delay
  • Branch penalty
  • None of the mentioned
Answer: Branch penalty
Q6 | The algorithm followed in most of the systems to perform out of order execution is ______
  • Tomasulo algorithm
  • Score carding
  • Reader-writer algorithm
  • None of the mentioned
Answer: Tomasulo algorithm
Q7 | The logic operations are implemented using _______ circuits.
  • Bridge
  • Logical
  • Combinatorial
  • Gate
Answer: Combinatorial
Q8 | The carry generation function: ci + 1 = yici + xici + xiyi, is implemented in ____________
  • Half adders
  • Full adders
  • Ripple adders
  • Fast adders
Answer: Full adders
Q9 | Which option is true regarding the carry in the ripple adders?
  • Are generated at the beginning only
  • Must travel through the configuration
  • Is generated at the end of each operation
  • None of the mentioned
Answer: Must travel through the configuration
Q10 | In full adders the sum circuit is implemented using ________
  • And & or gates
  • NAND gate
  • XOR
  • XNOR
Answer: XOR
Q11 | The usual implementation of the carry circuit involves _________
  • And & or gates
  • XOR
  • NAND
  • XNOR
Answer: XOR
Q12 | The advantage of I/O mapped devices to memory mapped is ___________
  • The former offers faster transfer of data
  • The devices connected using I/O mapping have a bigger buffer space
  • The devices have to deal with fewer address lines
  • No advantage as such
Answer: The devices have to deal with fewer address lines
Q13 | The system is notified of a read or write operation by ___________
  • Appending an extra bit of the address
  • Enabling the read or write bits of the devices
  • Raising an appropriate interrupt signal
  • Sending a special signal along the BUS
Answer: Sending a special signal along the BUS
Q14 | To overcome the lag in the operating speeds of the I/O device and the processor we use ___________
  • Buffer spaces
  • Status flags
  • Interrupt signals
  • Exceptions
Answer: Status flags
Q15 | The method which offers higher speeds of I/O transfers is ___________
  • Interrupts
  • Memory mapping
  • Program-controlled I/O
  • DMA
Answer: DMA
Q16 | The instruction, Add #45, R1 does _______
  • Adds the value of 45 to the address of R1 and stores 45 in that address
  • Adds 45 to the value of R1 and stores it in R1
  • Finds the memory location 45 and adds that content to that of R1
  • None of the mentioned
Answer: Adds 45 to the value of R1 and stores it in R1
Q17 | In the case of, Zero-address instruction method the operands are stored in _____
  • Registers
  • Accumulators
  • Push down stack
  • Cache
Answer: Push down stack
Q18 | The addressing mode which makes use of in-direction pointers is ______
  • Indirect addressing mode
  • Index addressing mode
  • Relative addressing mode
  • Offset addressing mode
Answer: Indirect addressing mode
Q19 | The addressing mode/s, which uses the PC instead of a general purpose register is ______
  • Indexed with offset
  • Relative
  • direct
  • both Indexed with offset and direct
Answer: Relative
Q20 | _____ addressing mode is most suitable to change the normal sequence of execution of instructions.
  • Relative
  • Indirect
  • Index with Offset
  • Immediate
Answer: Relative
Q21 | The reason for the implementation of the cache memory is ________
  • To increase the internal memory of the system
  • The difference in speeds of operation of the processor and memory
  • To reduce the memory access and cycle time
  • All of the mentioned
Answer: The difference in speeds of operation of the processor and memory
Q22 | The effectiveness of the cache memory is based on the property of ________
  • Locality of reference
  • Memory localisation
  • Memory size
  • None of the mentioned
Answer: Locality of reference
Q23 | The spatial aspect of the locality of reference means ________
  • That the recently executed instruction is executed again next
  • That the recently executed won’t be executed again
  • That the instruction executed will be executed at a later time
  • That the instruction in close proximity of the instruction executed will be executed in future
Answer: That the instruction in close proximity of the instruction executed will be executed in future
Q24 | The correspondence between the main memory blocks and those in the cache is given by _________
  • Hash function
  • Mapping function
  • Locale function
  • Assign function
Answer: Mapping function
Q25 | The copy-back protocol is used ________
  • To copy the contents of the memory onto the cache
  • To update the contents of the memory from the cache
  • To remove the contents of the cache and push it on to the memory
  • None of the mentioned
Answer: To update the contents of the memory from the cache
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