Computer Architecture Set 21

Computer Science Engineering (CSE)

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This set of Computer Architecture Multiple Choice Questions & Answers (MCQs) focuses on Computer Architecture Set 21

Q1 | To overcome the slow operating speeds of the secondary memory we make use of faster flash drives.
  • true
  • false
Answer: true
Explaination:
to improve the speed we use flash drives at the cost of memory space.
Q2 | The fastest data access is provided using                 
  • caches
  • dram’s
  • sram’s
  • registers
Answer: registers
Explaination:
the fastest data access is provided using registers as these memory locations are situated inside the processor.
Q3 | The memory which is used to store the copy of data or instructions stored in larger memories, inside the CPU is called                 
  • level 1 cache
  • level 2 cache
  • registers
  • tlb
Answer: level 1 cache
Explaination:
these memory devices are generally used to map onto the data stored in the larger memories.
Q4 | The larger memory placed between the primary cache and the memory is called               
  • level 1 cache
  • level 2 cache
  • eeprom
  • tlb
Answer: level 2 cache
Explaination:
this is basically used to provide effective memory mapping.
Q5 | The next level of memory hierarchy after the L2 cache is                 
  • secondary storage
  • tlb
  • main memory
  • register
Answer: register
Explaination:
none.
Q6 | The last on the hierarchy scale of memory devices is               
  • main memory
  • secondary memory
  • tlb
  • flash drives
Answer: secondary memory
Explaination:
the secondary memory is the slowest memory device.
Q7 | In the memory hierarchy, as the speed of operation increases the memory size also increases.
  • true
  • false
Answer: false
Explaination:
as the speed of operation increases the cost increases and the size decreases.
Q8 | If we use the flash drives instead of the harddisks, then the secondary storage can go above primary memory in the hierarchy.
  • true
  • false
Answer: false
Explaination:
the flash drives will increase the speed of transfer but still it won’t be faster than primary memory.
Q9 | The reason for the implementation of the cache memory is                   
  • to increase the internal memory of the system
  • the difference in speeds of operation of the processor and memory
  • to reduce the memory access and cycle time
  • all of the mentioned
Answer: the difference in speeds of operation of the processor and memory
Explaination:
this difference in the speeds of operation of the system caused it to be inefficient.
Q10 | The effectiveness of the cache memory is based on the property of
  • locality of reference
  • memory localisation
  • memory size
  • none of the mentioned
Answer: locality of reference
Explaination:
this means that the cache
Q11 | The temporal aspect of the locality of reference means                   
  • that the recently executed instruction won’t be executed soon
  • that the recently executed instruction is temporarily not referenced
  • that the recently executed instruction will be executed soon again
  • none of the mentioned
Answer: that the recently executed instruction will be executed soon again
Explaination:
none.
Q12 | The spatial aspect of the locality of reference means                   
  • that the recently executed instruction is executed again next
  • that the recently executed won’t be executed again
  • that the instruction executed will be executed at a later time
  • that the instruction in close proximity of the instruction executed will be executed in future
Answer: that the instruction in close proximity of the instruction executed will be executed in future
Explaination:
the spatial aspect of locality of reference tells that the nearby instruction is more likely to be executed in future.
Q13 | The correspondence between the main memory blocks and those in the cache is given by                     
  • hash function
  • mapping function
  • locale function
  • assign function
Answer: mapping function
Explaination:
the mapping function is used to map the contents of the memory to the cache.
Q14 | The algorithm to remove and place new contents into the cache is called
  • replacement algorithm
  • renewal algorithm
  • updation
  • none of the mentioned
Answer: replacement algorithm
Explaination:
as the cache gets full, older contents of the cache are swapped out with newer contents. this decision is taken by the algorithm.
Q15 | The write-through procedure is used
  • to write onto the memory directly
  • to write and read from memory simultaneously
  • to write directly on the memory and the cache simultaneously
  • none of the mentioned
Answer: to write directly on the memory and the cache simultaneously
Explaination:
when write operation is issued then the corresponding operation is performed.
Q16 | The bit used to signify that the cache location is updated is                   
  • dirty bit
  • update bit
  • reference bit
  • flag bit
Answer: dirty bit
Explaination:
when the cache location is updated in order to signal to the processor this bit is used.
Q17 | The copy-back protocol is used
  • to copy the contents of the memory onto the cache
  • to update the contents of the memory from the cache
  • to remove the contents of the cache and push it on to the memory
  • none of the mentioned
Answer: to update the contents of the memory from the cache
Explaination:
this is another way of performing the write operation, wherein the cache is updated first and then the memory.
Q18 | The approach where the memory contents are transferred directly to the processor from the memory is called
  • read-later
  • read-through
  • early-start
  • none of the mentioned
Answer: early-start
Explaination:
none.
Q19 | In                   protocol the information is directly written into the main memory.
  • write through
  • write back
  • write first
  • none of the mentioned
Answer: write through
Explaination:
in case of the miss, then the data gets written directly in main memory.
Q20 | The only draw back of using the early start protocol is                 
  • time delay
  • complexity of circuit
  • latency
  • high miss rate
Answer: complexity of circuit
Explaination:
in this protocol, the required block is read and directly sent to the processor.
Q21 | During a write operation if the required block is not present in the cache then               occurs.
  • write latency
  • write hit
  • write delay
  • write miss
Answer: write miss
Explaination:
this indicates that the
Q22 | While using the direct mapping technique, in a 16 bit system the higher order 5 bits are used for                   
  • tag
  • block
  • word
  • id
Answer: tag
Explaination:
the tag is used to identify the block mapped onto one particular cache block.
Q23 | In direct mapping the presence of the block in memory is checked with the help of block field.
  • true
  • false
Answer: false
Explaination:
the tag field is used to check the presence of a mem block.
Q24 | In associative mapping, in a 16 bit system the tag field has               bits.
  • 12
  • 8
  • 9
  • 10
Answer: 12
Explaination:
the tag field is used as an id for the different memory blocks mapped to the cache.
Q25 | The associative mapping is costlier than direct mapping.
  • true
  • false
Answer: true
Explaination:
in associative mapping, all the tags have to be searched to find the block.
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