Computer Architecture Set 19

Computer Science Engineering (CSE)

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This set of Computer Architecture Multiple Choice Questions & Answers (MCQs) focuses on Computer Architecture Set 19

Q1 | The capacitors lose the charge over time due to                   
  • the leakage resistance of the capacitor
  • the small current in the transistor after being turned on
  • the defect of the capacitor
  • none of the mentioned
Answer: the leakage resistance of the capacitor
Explaination:
the capacitor loses charge due to the backward current of the transistor and due to the small resistance.
Q2 |                     circuit is used to restore the capacitor value.
  • sense amplify
  • signal amplifier
  • delta modulator
  • none of the mentioned
Answer: sense amplify
Explaination:
the sense amplifier detects if the value is above or below the threshold and then restores it.
Q3 | To reduce the number of external connections required, we make use of
  • de-multiplexer
  • multiplexer
  • encoder
  • decoder
Answer: multiplexer
Explaination:
we multiplex the various address lines onto fewer pins.
Q4 | The processor must take into account the delay in accessing the memory location, such memories are called
  • delay integrated
  • asynchronous memories
  • synchronous memories
  • isochronous memories
Answer: asynchronous memories
Explaination:
none.
Q5 | To get the row address of the required data               is enabled.
  • cas
  • ras
  • cs
  • sense/write
Answer: ras
Explaination:
this makes the contents of the row required refreshed.
Q6 | In order to read multiple bytes of a row at the same time, we make use of
  • latch
  • shift register
  • cache
  • memory extension
Answer: latch
Explaination:
the latch makes it easy to ready multiple bytes of data of the same row simultaneously by just giving the consecutive column address.
Q7 | The block transfer capability of the DRAM is called                   
  • burst mode
  • block mode
  • fast page mode
  • fast frame mode
Answer: fast page mode
Explaination:
none.
Q8 | The difference between DRAM’s and SDRAM’s is/are                   
  • the dram’s will not use the master slave relationship in data transfer
  • the sdram’s make use of clock
  • the sdram’s are more power efficient
  • none of the mentioned
Answer: none of the mentioned
Explaination:
the sdram’s make use of clock signals to synchronize their operation.
Q9 | The difference in the address and data connection between DRAM’s and SDRAM’s is                 
  • the usage of more number of pins in sdram’s
  • the requirement of more address lines in sdram’s
  • the usage of a buffer in sdram’s
  • none of the mentioned
Answer: the usage of a buffer in sdram’s
Explaination:
the sdram uses buffered storage of address and data.
Q10 | A                 is used to restore the contents of the cells.
  • sense amplifier
  • refresh counter
  • restorer
  • none of the mentioned
Answer: refresh counter
Explaination:
the counter helps to restore the charge on the capacitor.
Q11 | The mode register is used to                 
  • select the row or column data transfer mode
  • select the mode of operation
  • select mode of storing the data
  • all of the mentioned
Answer: select the mode of operation
Explaination:
the mode register is used to choose between burst mode or bit mode of operation.
Q12 | In a SDRAM each row is refreshed every 64ms.
  • true
  • false
Answer: true
Explaination:
none.
Q13 | DDR SDRAM’s perform faster data transfer by                 
  • integrating the hardware
  • transferring on both edges
  • improving the clock speeds
  • increasing the bandwidth
Answer: transferring on both edges
Explaination:
by transferring data on both the edges the bandwidth is effectively doubled.
Q14 | To improve the data retrieval rate
  • access time
  • cycle time
  • memory latency
  • none of the mentioned
Answer: memory latency
Explaination:
the performance of the memory is measured by means of latency.
Q15 | In SDRAM’s buffers are used to store data that is read or written.
  • true
  • false
Answer: true
Explaination:
in sdram’s all the bytes of data to be read or written are stored in the buffer until the operation is complete.
Q16 | The SDRAM performs operation on the
  • rising edge of the clock
  • falling edge of the clock
  • middle state of the clock
  • transition state of the clock
Answer: rising edge of the clock
Explaination:
the sdram’s are edge-
Q17 | The chip can be disabled or cut off from an external connection using
  • chip select
  • lock
  • acpt
  • reset
Answer: chip select
Explaination:
the chip gets enabled if the cs is set otherwise the chip gets disabled.
Q18 | To organise large memory chips we make use of               
  • integrated chips
  • upgraded hardware
  • memory modules
  • none of the mentioned
Answer: memory modules
Explaination:
the cell blocks are arranged and put in a memory module.
Q19 | The less space consideration as lead to the development of                   (for large memories).
  • simm’s
  • dims’s
  • sram’s
  • both simm’s and dims’s
Answer: both simm’s and dims’s
Explaination:
the simm (single inline memory module) or dimm (dual inline memory module) occupy less space while providing greater memory space.
Q20 | The SRAM’s are basically used as
  • registers
  • caches
  • tlb
  • buffer
Answer: caches
Explaination:
the sram’s are used as caches as their operation speed is very high.
Q21 | The higher order bits of the address are used to            
  • specify the row address
  • specify the column address
  • input the cs
  • none of the mentioned
Answer: specify the row address
Explaination:
none.
Q22 | The address lines multiplexing is done using               
  • mmu
  • memory controller unit
  • page table
  • overlay generator
Answer: memory controller unit
Explaination:
this unit multiplexes the various address lines to lesser pins on the chip.
Q23 | The controller multiplexes the addresses after getting the            signal.
  • intr
  • ack
  • reset
  • request
Answer: request
Explaination:
the controller gets the request from the device needing the memory read or write operation and then it multiplexes the address.
Q24 | The RAS and CAS signals are provided by the               
  • mode register
  • cs
  • memory controller
  • none of the mentioned
Answer: memory controller
Explaination:
the multiplexed signal of the controller is split into ras and cas.
Q25 | When DRAM’s are used to build a complex large memory, then the controller only provides the refresh counter.
  • true
  • false
Answer: true
Explaination:
none.
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