Computer Architecture Set 24

Computer Science Engineering (CSE)

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This set of Computer Architecture Multiple Choice Questions & Answers (MCQs) focuses on Computer Architecture Set 24

Q1 | Every time a new instruction is loaded into IR the output of                   is loaded into UPC.
  • starting address generator
  • loader
  • linker
  • clock
Answer: starting address generator
Explaination:
the starting address generator is used to load the address of the next micro instruction.
Q2 | The case/s where micro-programmed can perform well                                 
  • when it requires to check the condition codes
  • when it has to choose between the two alternatives
  • when it is triggered by an interrupt
  • none of the mentioned
Answer: none of the mentioned
Explaination:
none.
Q3 | The signals are grouped such that mutually exclusive signals are put together.
  • true
  • false
Answer: true
Explaination:
this is done to improve the efficiency of the controller.
Q4 | Highly encoded schemes that use compact codes to specify a small number of functions in each micro instruction is                   
  • horizontal organisation
  • vertical organisation
  • diagonal organisation
  • none of the mentioned
Answer: vertical organisation
Explaination:
none.
Q5 | The directly mapped cache no replacement algorithm is required.
  • true
  • false
Answer: true
Explaination:
the position of each block is pre-determined in the direct mapped cache, hence no need for replacement.
Q6 | In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one when            occurs.
  • delay
  • miss
  • hit
  • delayed hit
Answer: miss
Explaination:
miss usually occurs when the memory block required is not present in the cache.
Q7 | In set associative and associative mapping there exists less flexibility.
  • true
  • false
Answer: false
Explaination:
the above two methods of mapping the decision of which block to be removed rests with the cache controller.
Q8 | The algorithm which replaces the block which has not been referenced for a while is called            
  • lru
  • orf
  • direct
  • both lru and orf
Answer: lru
Explaination:
lru stands for least recently used first.
Q9 | The algorithm which removes the recently used page first is                   
  • lru
  • mru
  • ofm
  • none of the mentioned
Answer: mru
Explaination:
in mru it is assumed that the page accessed now is less likely to be accessed again.
Q10 | The LRU can be improved by providing a little randomness in the access.
  • true
  • false
Answer: true
Explaination:
none.
Q11 | In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are incremented by one and others remain same, in the case of
  • hit
  • miss
  • delay
  • none of the mentioned
Answer: hit
Explaination:
if the referenced block is present in the memory it is called as a hit.
Q12 | The counter that keeps track of how many times a block is most likely used is
  • count
  • reference counter
  • use counter
  • probable counter
Answer: reference counter
Explaination:
none.
Q13 | The key factor/s in commercial success of a computer is/are                   
  • performance
  • cost
  • speed
  • both performance and cost
Answer: both performance and cost
Explaination:
the performance and cost of the computer system is a key decider in the commercial success of the system.
Q14 | A common measure of performance is
  • price/performance ratio
  • performance/price ratio
  • operation/price ratio
  • none of the mentioned
Answer: price/performance ratio
Explaination:
if this measure is less than one then the system is optimal.
Q15 | The performance depends on
  • the speed of execution only
  • the speed of fetch and execution
  • the speed of fetch only
  • the hardware of the system only
Answer: the speed of fetch and execution
Explaination:
the performance of a system is decided by how quick an instruction is brought into the system and executed.
Q16 | The main purpose of having memory hierarchy is to                   
  • reduce access time
  • provide large capacity
  • reduce propagation time
  • reduce access time & provide large capacity
Answer: reduce access time & provide large capacity
Explaination:
by using the memory hierarchy, we can increase the performance of the system.
Q17 | The memory transfers between two variable speed devices are always done at the speed of the faster device.
  • true
  • false
Answer: true
Explaination:
none.
Q18 | An effective to introduce parallelism in memory access is by                 
  • memory interleaving
  • tlb
  • pages
  • frames
Answer: memory interleaving
Explaination:
interleaving divides the memory into modules.
Q19 | The performance of the system is greatly influenced by increasing the level 1 cache.
  • true
  • false
Answer: true
Explaination:
this is so because the l1 cache is onboard the processor.
Q20 | Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster.
  • a
  • b
  • both take the same time
  • insufficient information
Answer: a
Explaination:
none.
Q21 | If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the value of S is (Where S is a term of the Basic performance equation).
  • 3
  • ~2
  • ~1
  • 6
Answer: ~1
Explaination:
pipelining is a process of fetching an instruction during the execution of other instruction.
Q22 | The physical memory is not as large as the address space spanned by the processor.
  • true
  • false
Answer: true
Explaination:
this is one of the main reasons for the usage of virtual memories.
Q23 | The program is divided into operable parts called as                     
  • frames
  • segments
  • pages
  • sheets
Answer: segments
Explaination:
the program is divided into parts called as segments for ease of execution.
Q24 | The techniques which move the program blocks to or from the physical memory is called as               
  • paging
  • virtual memory organisation
  • overlays
  • framing
Answer: virtual memory organisation
Explaination:
by using this technique the program execution is accomplished with a usage of less space.
Q25 | The binary address issued to data or instructions are called as               
  • physical address
  • location
  • relocatable address
  • logical address
Answer: logical address
Explaination:
the logical address is the random address generated by the processor.
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