Digital Principles And System Design Set 26 MCQs

This set of Digital Principles and System Design Multiple Choice Questions & Answers (MCQs) focuses on Digital Principles And System Design Set 26

Q1 | How many 16K * 4 RAMs are required to achieve a memory with a capacity of 64K and a word length of 8 bits?

Q2 | Why antifuses are implemented in a PLD?

to protect from high voltage

to increase the memory

to implement the programmes

as a switching devices

Q3 | How many types of PLD is?

Q4 | PLA refers to

programmable loaded array

programmable array logic

programmable logic array

programmed array logic

Q5 | The inputs in the PLD is given through

nand gates

or gates

nor gates

and gates

Q6 | PAL refers to

programmable array loaded

programmable logic array

programmable array logic

programmable and logic

Q7 | Outputs of the AND gate in PLD is known as

input lines

output lines

strobe lines

control lines

Q8 | PLA contains

and and or arrays

nand and or arrays

not and and arrays

nor and or arrays

Q9 | PLA is used to implement

a complex sequential circuit

a simple sequential circuit

a complex combinational circuit

a simple combinational circuit

Q10 | A PLA is similar to a ROM in concept except that

it hasn’t capability to read only

it hasn’t capability to read or write operation

it doesn’t provide full decoding to the variables

it hasn’t capability to write only

Q11 | 6 PROGRAMMABLE ARRAY LOGIC

pla

pal

cpld

sld

Q12 | The complex programmable logic device contains several PLD blocks and

a language compiler

and/or arrays

global interconnection matrix

field-programmable switches

Q13 | Which type of device FPGA are?

sld

srom

eprom

pld

Q14 | The difference between a PAL & a PLA is

pals and plas are the same thing

the pla has a programmable or plane and a programmable and plane, while the pal only has a programmable and plane

the pal has a programmable or plane and a programmable and plane, while the pla only has a programmable and plane

the pal has more possible product terms than the pla

Q15 | If a PAL has been programmed once

its logic capacity is lost

its outputs are only active high

its outputs are only active low

it cannot be reprogrammed

Q16 | The FPGA refers to

first programmable gate array

field programmable gate array

first program gate array

field program gate array

Q17 | The full form of VLSI is

very long single integration

very least scale integration

very large scale integration

very long scale integration

Q18 | In FPGA, vertical and horizontal directions are separated by

a line

a channel

a strobe

a flip-flop

Q19 | Applications of PLAs are

registered pals

configurable pals

pal programming

all of the mentioned

Q20 | For programmable logic functions, which type of PLD should be used?

pla

pal

cpld

sld