Digital Principles And System Design Set 8

Computer Science Engineering (CSE)

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This set of Digital Principles and System Design Multiple Choice Questions & Answers (MCQs) focuses on Digital Principles And System Design Set 8

Q1 | A 4 to 16 decoder can be used as a code converter. What will be the inputs and outputs of the converter respectively?
  • binary, octal
  • octal, binary
  • hexadecimal, binary
  • binary, hexadecimal
Answer: hexadecimal, binary
Explaination:
since, 24 = 16, therefore, the decoder can act as hexadecimal to binary converter. because, 4 bits input is converted to 16 bits output. each bit corresponding to 4 output bits. so, clearly it is a hexadecimal to binary convertor.
Q2 | Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?
  • low input voltages
  • synchronous operation
  • gate impedance
  • cross coupling
Answer: cross coupling
Explaination:
latch is a type of bistable multivibrator having two stable states. both inputs of a latch are directly connected to the other’s output. such types of structure is called cross coupling and due to which latches remain in the latched condition.
Q3 | One example of the use of an S-R flip-flop is as
  • transition pulse generator
  • racer
  • switch debouncer
  • astable oscillator
Answer: switch debouncer
Explaination:
the sr flip-flop is very effective in removing the effects of switch bounce, which is the unwanted noise caused during the switching of electronic devices.
Q4 | The truth table for an S-R flip-flop has how many VALID entries?
  • 1
  • 2
  • 3
  • 4
Answer: 3
Explaination:
the sr flip-flop actually has three inputs, set, reset and its current state. the invalid or undefined state occurs at both s and r being at 1.
Q5 | When both inputs of a J-K flip-flop cycle, the output will                        
  • be invalid
  • change
  • not change
  • toggle
Answer: not change
Explaination:
after one cycle the value of each input comes to the same value. eg: assume j=0 and k=1. after 1 cycle, it becomes as j=0->1->0(1 cycle complete) and k=1->0->1(1 cycle complete). the j & k flip-flop has 4 stable states: latch, reset, set and toggle.
Q6 | Which of the following is correct for a gated D-type flip-flop?
  • the q output is either set or reset as soon as the d input goes high or low
  • the output complement follows the input when enabled
  • only one of the inputs can be high at a time
  • the output toggles if one of the inputs is held high
Answer: the q output is either set or reset as soon as the d input goes high or low
Explaination:
in d flip flop, when the clock is high then the output depends on the input otherwise reminds previous output. in a state of clock high, when d is high the output q also high, if d is ‘0’ then output is also zero. like sr flip-flop, the d-flip-flop also have an invalid state at both inputs being 1.
Q7 | A basic S-R flip-flop can be constructed by cross- coupling of which basic logic gates?
  • and or or gates
  • xor or xnor gates
  • nor or nand gates
  • and or nor gates
Answer: nor or nand gates
Explaination:
the basic s-r flip-flop can be constructed by cross coupling of nor or nand gates. cross coupling means the output of second gate is fed to the input of first gate and vice-versa.
Q8 | The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called
  • combinational circuits
  • sequential circuits
  • latches
  • flip-flops
Answer: sequential circuits
Explaination:
in sequential circuits, the output signals
Q9 | Whose operations are more faster among the following?
  • combinational circuits
  • sequential circuits
  • latches
  • flip-flops
Answer: combinational circuits
Explaination:
combinational circuits are often faster than sequential circuits. since, the combinational circuits do not require memory elements whereas the sequential circuits need memory devices to perform their operations in sequence. latches and flip-flops come under sequential circuits.
Q10 | How many types of sequential circuits are?
  • 2
  • 3
  • 4
  • 5
Answer: 2
Explaination:
there are two type of sequential circuits viz., (i) synchronous or clocked and (ii) asynchronous or unclocked. synchronous sequential circuits are triggered in the presence of a clock signal, whereas, asynchronous sequential circuits function in the absence of a clock signal.
Q11 | The sequential circuit is also called                        
  • flip-flop
  • latch
  • strobe
  • adder
Answer: latch
Explaination:
the sequential circuit is also called a latch because both are a memory cell, which are capable of storing one bit of information.
Q12 | The basic latch consists of                        
  • two inverters
  • two comparators
  • two amplifiers
  • two adders
Answer: two inverters
Explaination:
the basic latch consists of two inverters.
Q13 | In S-R flip-flop, if Q = 0 the output is said to be
  • set
  • reset
  • previous state
  • current state
Answer: reset
Explaination:
in s-r flip-flop, if q = 0 the output is said to be reset and set for q = 1.
Q14 | The output of latches will remain in set/reset untill
  • the trigger pulse is given to change the state
  • any pulse given to go into previous state
  • they don’t get any pulse more
  • the pulse is edge-triggered
Answer: the trigger pulse is given to change the state
Explaination:
the output of latches will remain in set/reset untill the trigger pulse is given to change the state.
Q15 | What is a trigger pulse?
  • a pulse that starts a cycle of operation
  • a pulse that reverses the cycle of operation
  • a pulse that prevents a cycle of operation
  • a pulse that enhances a cycle of operation
Answer: a pulse that starts a cycle of operation
Explaination:
trigger pulse is defined as a pulse that starts a cycle of operation.
Q16 | The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why?
  • because of inverted outputs
  • because of triggering functionality
  • because of cross-coupled connection
  • because of inverted outputs & triggering functionality
Answer: because of cross-coupled connection
Explaination:
the cross-coupled connections from the output of one gate to the input of the other gate constitute a feedback path. for this reason, the circuits of nor based s-r latch classified as asynchronous sequential circuits. moreover, they are referred to as asynchronous because they function in the absence of a clock pulse.
Q17 | A latch is an example of a                        
  • monostable multivibrator
  • astable multivibrator
  • bistable multivibrator
  • 555 timer
Answer: bistable multivibrator
Explaination:
a latch is an example of a bistable multivibrator. a bistable multivibrator is one in which the circuit is stable in either of two states. it can be flipped from one state to the other state and vice-versa.
Q18 | Latch is a device with                        
  • one stable state
  • two stable state
  • three stable state
  • infinite stable states
Answer: two stable state
Explaination:
since, a latch works on the principal of bistable multivibrator. a bistable multivibrator is one in which the circuit is stable in either of two states. it can be flipped from one state to the other state and vice-versa. so a latch has two stable states.
Q19 | Why latches are called a memory devices?
  • it has capability to stare 8 bits of data
  • it has internal memory of 4 bit
  • it can store one bit of data
  • it can store infinite amount of data
Answer: it can store one bit of data
Explaination:
latches can be memory devices, and can store one bit of data for as long as the device is powered. once device is turned off, the memory gets refreshed.
Q20 | Two stable states of latches are                        
  • astable & monostable
  • low input & high output
  • high output & low output
  • low output & high input
Answer: high output & low output
Explaination:
a latch has two stable states, following the principle of bistable multivibrator. there are two stable states of latches and these states are high-output and low-output.
Q21 | The full form of SR is                        
  • system rated
  • set reset
  • set ready
  • set rated
Answer: set reset
Explaination:
the full form of sr is set/reset. it is a type of latch having two stable states.
Q22 | The SR latch consists of                        
  • 1 input
  • 2 inputs
  • 3 inputs
  • 4 inputs
Answer: 2 inputs
Explaination:
sr or set-reset latch is the simplest type of bistable multivibrator having two stable states. the diagram of sr latch is shown below:
Q23 | The outputs of SR latch are                        
  • x and y
  • a and b
  • s and r
  • q and q’
Answer: q and q’
Explaination:
sr or set-reset latch is the simplest type of bistable multivibrator having two stable states. the inputs of sr latch are s and r while outputs are q
Q24 | The NAND latch works when both inputs are
  • 1
  • 0
  • inverted
  • don’t cares
Answer: 1
Explaination:
the nand latch works when both inputs are 1. since, both of the inputs are inverted in a nand latch.
Q25 | The first step of analysis procedure of SR latch is to                        
  • label inputs
  • label outputs
  • label states
  • label tables
Answer: label outputs
Explaination:
all flip flops have at least one output labeled q (i.e. inverted). this is so because the flip flops have inverting gates inside them, hence in order to have both q and q complement available, we have atleast one output labelled.
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