Digital Principles And System Design Set 23
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This set of Digital Principles and System Design Multiple Choice Questions & Answers (MCQs) focuses on Digital Principles And System Design Set 23
Q1 | Which of the following attribute is generally used in implementation of sequential circuits?
- ‘stable
- ‘length
- ‘last_event
- ‘event
Q2 | Which of the following line is correct for detecting positive edge of a clock?
- if (clk’event and clk = ‘0’)
- if (clk’event and clk = ‘1’)
- if (clk’event or clk = ‘0’)
- if (clk’event or clk = ‘1’)
Q3 | A user doesn’t want to use the IF statement for detecting clock edge. It is possible to do the same by using any other keyword in VHDL.
- true
- false
Q4 | Sequential circuits are represented as
- finite state machine
- infinite state machine
- finite synchronous circuit
- infinite asynchronous circuit
Q5 | Sequential circuit includes
- delays
- feedback
- delays and feedback from input to output
- delays and feedback from output to input
Q6 | Which constitutes the test vectors in sequential circuits?
- feedback variables
- delay factors
- test patterns
- all input combinations
Q7 | Outputs are functions of
- present state
- previous state
- next state
- present and next state
Q8 | Which is the delay elements for clocked system?
- and gates
- or gates
- flip-flops
- multiplexers
Q9 | Which contributes to the necessary delay element?
- flip-flops
- circuit propagation elements
- negative feedback path
- shift registers
Q10 | In an OR gate, if A and B are two inputs and there is struck at 1 fault in B path, then output will be
- a
- 0
- 1
- b’
Q11 | Iterative test generation method suits for circuits with
- no feedback loops
- few feedback loops
- more feedback loops
- negative feedback loops only
Q12 | Which method is very time consuming?
- d-algorithm
- iterative test generation
- pseudo exhaustive method
- test generation pattern
Q13 | In this iterative test generation method, sequential logic is
- used in the same pattern
- converted to test logic
- converted to combinational logic
- converted to asynchronous logic
Q14 | For a NAND gate, struck-at 1 fault in second input line cannot be detected if
- q is 1
- q is 0
- q changes from 1 to 0
- q changes from 0 to 1
Q15 | Any condition that causes a processor to stall is called as
- hazard
- page fault
- system error
- none of the mentioned
Q16 | In this technique, a simple fault manifests into multiple N faults.
- true
- false
Q17 | The contention for the usage of a hardware device is called
- structural hazard
- stalk
- deadlock
- none of the mentioned
Q18 | The situation wherein the data of operands are not available is called
- data hazard
- stock
- deadlock
- structural hazard
Q19 | The stalling of the processor due to the unavailability of the instructions is called as
- control hazard
- structural hazard
- input hazard
- none of the mentioned
Q20 | The time lost due to the branch instruction is often referred to as
- latency
- delay
- branch penalty
- none of the mentioned
Q21 | method is used in centralized systems to perform out of order execution.
- scorecard
- score boarding
- optimizing
- redundancy
Q22 | The algorithm followed in most of the systems to perform out of order execution is
- tomasulo algorithm
- score carding
- reader-writer algorithm
- none of the mentioned
Q23 | The problem where process concurrency becomes an issue is called as
- philosophers problem
- bakery problem
- bankers problem
- reader-writer problem
Q24 | What are the typical values of tOE?
- 10 to 20 ns for bipolar
- 25 to 100 ns for nmos
- 12 to 50 ns for cmos
- all of the mentioned
Q25 | Which of the following is not a type of memory?
- ram
- fprom
- eeprom
- rom