Digital Principles And System Design Set 10

Computer Science Engineering (CSE)

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This set of Digital Principles and System Design Multiple Choice Questions & Answers (MCQs) focuses on Digital Principles And System Design Set 10

Q1 | A user has designed JK flip flop by using the VHDL code. The output is continuously switching between 0 and 1. This condition is known as                
  • switching condition
  • master slave condition
  • race around condition
  • edge triggered condition
Answer: race around condition
Explaination:
this continuous switching of output between 0 and 1 may be the result of toggle state of the flip flop. this occurs when both the inputs j and k are high and the output toggles its previous state. this condition is called the race around the condition.
Q2 | Which of the following method is not used to remove the race around condition in a flip flop?
  • using level triggered flip flop
  • using master slave flip flop
  • using edge triggered flip flop
  • all of the above are used to remove the race around
Answer: using level triggered flip flop
Explaination:
the race around condition in jk flip flop can be removed by two methods which are using edge triggered flip flop and by using master slave flip flop. however, using level triggered flip flop cause the race around condition.
Q3 | Which of the following attribute is generally used in implementation of sequential circuits?
  • ‘stable
  • ‘length
  • ‘last_event
  • ‘event
Answer: ‘event
Explaination:
generally ‘event attribute is used in implementation of sequential circuits, because sequential circuit makes use of clock signal which needs to be detected at every positive or negative edge.
Q4 | Which of the following line is correct for detecting positive edge of a clock?
  • if (clk’event and clk = ‘0’)
  • if (clk’event and clk = ‘1’)
  • if (clk’event or clk = ‘0’)
  • if (clk’event or clk = ‘1’)
Answer: if (clk’event and clk = ‘1’)
Explaination:
the correct way to identify the positive edge of the clock signal is shown in option b. the ‘event attribute will detect the event and clk = ‘1’ will check whether its high on clock or not. in this way the positive edge is monitored. we need to use and operator because both of the conditions should be true.
Q5 | A user doesn’t want to use the IF statement for detecting clock edge. It is possible to do the same by using any other keyword in VHDL.
  • true
  • false
Answer: true
Explaination:
it is completely possible to detect the clock edge (positive or negative) by any other method than if statement. one can use the wait statement to detect either of the edge of the clock pulse.
Q6 | Sequential circuits are represented as
  • finite state machine
  • infinite state machine
  • finite synchronous circuit
  • infinite asynchronous circuit
Answer: finite state machine
Explaination:
sequential circuits are represented as finite state machine and may be modelled as combinational logic.
Q7 | Sequential circuit includes
  • delays
  • feedback
  • delays and feedback from input to output
  • delays and feedback from output to input
Answer: delays and feedback from output to input
Explaination:
sequential circuit includes a set of delays and feedback from output to input and it is known as finite state machine.
Q8 | Which constitutes the test vectors in sequential circuits?
  • feedback variables
  • delay factors
  • test patterns
  • all input combinations
Answer: feedback variables
Explaination:
the ‘m’ feedback variables constitute the state vector and determine the maximum number of finite states which may be assumed by the circuit.
Q9 | Outputs are functions of
  • present state
  • previous state
  • next state
  • present and next state
Answer: present state
Explaination:
next state and output are both functions of present state and the independent inputs.
Q10 | Which is the delay elements for clocked system?
  • and gates
  • or gates
  • flip-flops
  • multiplexers
Answer: flip-flops
Explaination:
in clocked systems, the basic delay elements are flip-flops and in asynchronous circuits, the delays may be contributed by circuit propagation delays.
Q11 | Which contributes to the necessary delay element?
  • flip-flops
  • circuit propagation elements
  • negative feedback path
  • shift registers
Answer: circuit propagation elements
Explaination:
the circuit propagation delays contribute to the necessary delay elements. the delay in the feedback path may be non-existence.
Q12 | In an OR gate, if A and B are two inputs and there is struck at 1 fault in B path, then output will be
  • a
  • 0
  • 1
  • b’
Answer: 1
Explaination:
in an or gate, if struck at 1 fault in present in b path then output will always be 1.
Q13 | Iterative test generation method suits for circuits with
  • no feedback loops
  • few feedback loops
  • more feedback loops
  • negative feedback loops only
Answer: few feedback loops
Explaination:
the iterative test generation methods are best suited to logic with few feedback loops as in control logic for example.
Q14 | Which method is very time consuming?
  • d-algorithm
  • iterative test generation
  • pseudo exhaustive method
  • test generation pattern
Answer: iterative test generation
Explaination:
iterative test generation method is time consuming for circuits of any complexity. it is
Q15 | In this iterative test generation method, sequential logic is
  • used in the same pattern
  • converted to test logic
  • converted to combinational logic
  • converted to asynchronous logic
Answer: converted to combinational logic
Explaination:
in this iterative test generation method, the main approach of testing is sequential logic is converted into combinational logic by cutting the feedback lines, thus creating pesudo inputs and outputs.
Q16 | For a NAND gate, struck-at 1 fault in second input line cannot be detected if
  • q is 1
  • q is 0
  • q changes from 1 to 0
  • q changes from 0 to 1
Answer: q is 0
Explaination:
in a nand gate, struck-at 1 fault in the second input line cannot be detected if the output q is reset (q=0) prior to applying the test sequence.
Q17 | Any condition that causes a processor to stall is called as                    
  • hazard
  • page fault
  • system error
  • none of the mentioned
Answer: hazard
Explaination:
an hazard causes a delay in the execution process of the processor.
Q18 | In this technique, a simple fault manifests into multiple N faults.
  • true
  • false
Answer: true
Explaination:
the main problem in this iterative test generation technique is that a simple fault in the sequential machine is manifest as n multiple faults during test.
Q19 | The contention for the usage of a hardware device is called              
  • structural hazard
  • stalk
  • deadlock
  • none of the mentioned
Answer: structural hazard
Explaination:
the processor contends for the usage of the hardware and might enter into a deadlock state.
Q20 | The situation wherein the data of operands are not available is called              
  • data hazard
  • stock
  • deadlock
  • structural hazard
Answer: data hazard
Explaination:
data hazards are generally caused when the data is not ready on the destination side.
Q21 | The stalling of the processor due to the unavailability of the instructions is called as
  • control hazard
  • structural hazard
  • input hazard
  • none of the mentioned
Answer: control hazard
Explaination:
the control hazard also called as instruction hazard is usually caused by a cache miss.
Q22 | The time lost due to the branch instruction is often referred to as                          
  • latency
  • delay
  • branch penalty
  • none of the mentioned
Answer: branch penalty
Explaination:
this time also retards the performance speed of the processor.
Q23 |                          method is used in centralized systems to perform out of order execution.
  • scorecard
  • score boarding
  • optimizing
  • redundancy
Answer: score boarding
Explaination:
in a scoreboard, the data dependencies of every instruction are logged. instructions are released only when the scoreboard determines that there are no conflicts with previously issued and incomplete instructions.
Q24 | The algorithm followed in most of the systems to perform out of order execution is                      
  • tomasulo algorithm
  • score carding
  • reader-writer algorithm
  • none of the mentioned
Answer: tomasulo algorithm
Explaination:
the tomasulo algorithm is a hardware algorithm developed in 1967 by robert tomasulo from ibm. it allows sequential instructions that would normally be stalled due to certain dependencies to execute non-sequentially (out-of-order execution).
Q25 | The problem where process concurrency becomes an issue is called as                        
  • philosophers problem
  • bakery problem
  • bankers problem
  • reader-writer problem
Answer: reader-writer problem
Explaination:
none.
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