Digital Principles And System Design Set 22

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This set of Digital Principles and System Design Multiple Choice Questions & Answers (MCQs) focuses on Digital Principles And System Design Set 22

Q1 | When both inputs of SR latches are low, the latch
  • q output goes high
  • q’ output goes high
  • it remains in its previously set or reset state
  • it goes to its next set or reset state
Q2 | When both inputs of SR latches are high, the latch goes                        
  • unstable
  • stable
  • metastable
  • bistable
Q3 | The register is a type of                        
  • sequential circuit
  • combinational circuit
  • cpu
  • latches
Q4 | How many types of registers are?
  • 2
  • 3
  • 4
  • 5
Q5 | The main difference between a register and a counter is                        
  • a register has no specific sequence of states
  • a counter has no specific sequence of states
  • a register has capability to store one bit of information but counter has n-bit
  • a register counts data
Q6 | In serial shifting method, data shifting occurs
  • universal shift register
  • unidirectional shift register
  • unipolar shift register
  • unique shift register
Q7 | A register that is used to store binary information is called                        
  • data register
  • binary register
  • shift register
  • d – register
Q8 | A shift register is defined as                        
  • the register capable of shifting information to another register
  • the register capable of shifting information either to the right or to the left
  • the register capable of shifting information to the right only
  • the register capable of shifting information to the left only
Q9 | In digital logic, a counter is a device which
  • counts the number of outputs
  • stores the number of times a particular event or process has occurred
  • stores the number of times a clock pulse rises and falls
  • counts the number of inputs
Q10 | A counter circuit is usually constructed of
  • a number of latches connected in cascade form
  • a number of nand gates connected in cascade form
  • a number of flip-flops connected in cascade
  • a number of nor gates connected in cascade form
Q11 | 4 COUNTERS
  • 0 to 2n
  • 0 to 2n + 1
  • 0 to 2n – 1 d) 0 to 2n+1/2
Q12 | How many types of the counter are there?
  • 2
  • 3
  • 4
  • 5
Q13 | A decimal counter has              states.
  • 5
  • 10
  • 15
  • 20
Q14 | Ripple counters are also called                          
  • ssi counters
  • asynchronous counters
  • synchronous counters
  • vlsi counters
Q15 | Synchronous counter is a type of                          
  • ssi counters
  • lsi counters
  • msi counters
  • vlsi counters
Q16 | Three decade counter would have                          
  • 2 bcd counters
  • 3 bcd counters
  • 4 bcd counters
  • 5 bcd counters
Q17 | BCD counter is also known as                          
  • parallel counter
  • decade counter
  • synchronous counter
  • vlsi counter
Q18 | The parallel outputs of a counter circuit represent the                            
  • parallel data word
  • clock frequency
  • counter modulus
  • clock count
Q19 | A sequential logic can’t be executed by concurrent statements only.
  • true
  • false
Q20 | Which of the following sequential circuit doesn’t need a clock signal?
  • flip flop
  • asynchronous counter
  • shift register
  • latch
Q21 | The following timing diagram shows              flip flop.
  • t flip-flop
  • d flip-flop
  • sr flip-flop
  • jk flip-flop
Q22 | The process used for implementation of sequential logic in VHDL is called              process.
  • sequential process
  • combinational process
  • clocked process
  • unclocked process
Q23 | Why do we need to define clock signal in the sensitivity list of the process?
  • to trigger the statement as soon as there is some event on clock
  • to trigger the clock signal as soon as there is some event on input
  • to trigger the clock signal as soon as there is some event on output
  • to trigger the statement as soon as there is some event on input
Q24 | A user has designed JK flip flop by using the VHDL code. The output is continuously switching between 0 and 1. This condition is known as                
  • switching condition
  • master slave condition
  • race around condition
  • edge triggered condition
Q25 | Which of the following method is not used to remove the race around condition in a flip flop?
  • using level triggered flip flop
  • using master slave flip flop
  • using edge triggered flip flop
  • all of the above are used to remove the race around