Digital Principles And System Design Set 20

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This set of Digital Principles and System Design Multiple Choice Questions & Answers (MCQs) focuses on Digital Principles And System Design Set 20

Q1 | How many NOT gates are required for the construction of a 4-to-1 multiplexer?
Q2 | In the given 4-to-1 multiplexer, if c1 = 0 and c0 = 1 then the output M is                        
Q3 | The enable input is also known as                        
Q4 | The full form of HDL is                                    
Q5 | The full form of VHDL is                            
Q6 | VHSIC stands for                            
Q7 | VHDL is being used for                            
Q8 | The use of VHDL can be done in            ways.
Q9 | At high frequencies when the sampling interval is too long in a frequency counter                            
Q10 | The output frequency related to the sampling interval of a frequency counter as                            
Q11 | In an HDL application of a stepper motor, what is done next after an up/down counter is built?
Q12 | In a digital clock application, the basic frequency must be divided down as                            
Q13 | What does the data signal do in the keypad application?
Q14 | When a key is pressed, what does the ring counter in the HDL keypad application do?
Q15 | A step which should be followed in project management is known as                            
Q16 | In the keypad application, the preset state of the ring counter define                            
Q17 | A major block which is not a part of an HDL frequency counter                            
Q18 | A stepper motor HDL application must include
Q19 | Which of the following is a not a characteristics of combinational circuits?
Q20 | 11 HDL MODELS OF COMBINATIONAL CIRCUITS
Q21 | Which of the following is not a combinational circuit?
Q22 | In a given combinational circuit, the concurrent statements are used with selected assignments using WHEN and ELSE keyword. What is the other alternative to implement the same?
Q23 | For using a process to implement a combinational circuit, which signals should be in the sensitivity list?
Q24 | A 4 to 16 decoder can be used as a code converter. What will be the inputs and outputs of the converter respectively?
Q25 | Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?