Digital Principles And System Design Set 17 MCQs

Q1 | What is the indication of a short to ground in the output of a driving gate?

only the output of the defective gate is affected

there is a signal loss to all load gates

the node may be stuck in either the high or the low state

the affected node will be stuck in the high state

Q2 | For the device shown here, assume the D input is LOW, both S inputs are LOW and the input is LOW. What is the status of the Y’ outputs?

d

a

c

b

Q3 | Which of the following combinations of logic gates can decode binary 1101?

one 4-input and gate

one 4-input and gate, one inverter

one 4-input and gate, one or gate

one 4-input nand gate, one inverter

Q4 | The carry propagation can be expressed as

cp = ab

cp = a + b

all but y0 are low

all but y0 are high

Q5 | 3 bits full adder contains

3 combinational inputs

4 combinational inputs

6 combinational inputs

8 combinational inputs

Q6 | The basic building blocks of the arithmetic unit in a digital computers are

subtractors

adders

multiplexer

comparator

Q7 | A digital system consists of types of circuits.

2

3

4

5

Q8 | In a sequential circuit, the output at any time depends only on the input values at that time.

past output values

intermediate values

both past output and present input

present input values

Q9 | The design of an ALU is based on

sequential logic

combinational logic

multiplexing

de-multiplexing

Q10 | If the two numbers are unsigned, the bit conditions of interest are the carry and a possible result.

input, zero

output, one

input, one

output, zero

Q11 | If the two numbers include a sign bit in the highest order position, the bit conditions of interest are the sign of the result, a zero indication and

an underflow condition

a neutral condition

an overflow condition

one indication

Q12 | The flag bits in an ALU is defined as

the total number of registers

the status bit conditions

the total number of control lines

all of the mentioned

Q13 | In parts of the processor, adders are used to calculate

addresses

table indices

increment and decrement operators

all of the mentioned

Q14 | Total number of inputs in a half adder is

2

3

4

1

Q15 | In which operation carry is obtained?

subtraction

addition

multiplication

both addition and subtraction

Q16 | If A and B are the inputs of a half adder, the carry is given by

a and b

a or b

a xor b

a ex-nor b

Q17 | Half-adders have a major limitation in that they cannot

accept a carry bit from a present stage

accept a carry bit from a next stage

accept a carry bit from a previous stage

accept a carry bit from the following stages

Q18 | If A, B and C are the inputs of a full adder then the carry is given by

a and b or (a or b) and c

a or b or (a and b) c

(a and b) or (a and b)c

a xor b xor (a xor b) and c

Q19 | How many AND, OR and EXOR gates are required for the configuration of full adder?

1, 2, 2

2, 1, 2

3, 1, 2

4, 0, 1

Q20 | How many outputs are required for the implementation of a subtractor?

1

2

3

4

Q21 | Let the input of a subtractor is A and B then what the output will be if A = B?

0

1

a

b

Q22 | Let A and B is the input of a subtractor then the output will be

a xor b

a and b

a or b

a exnor b

Q23 | Let A and B is the input of a subtractor then the borrow will be

a and b’

a’ and b

a or b

a and b

Q24 | The full subtractor can be implemented using

two xor and an or gates

two half subtractors and an or gate

two multiplexers and an and gate

two comparators and an and gate

Q25 | The output of a subtractor is given by (if A, B and X are the inputs).

a and b xor x

a xor b xor x

a or b nor x

a nor b xor x