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This set of Digital Logic Circuits DLC Multiple Choice Questions & Answers (MCQs) focuses on Digital Logic Circuits Set 5
Q1 | A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
- and or or gates
- xor or xnor gates
- nor or nand gates
- and or nor gates
Q2 | The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called
- combinational circuits
- sequential circuits
- latches
- flip-flops
Q3 | Whose operations are more faster among the following?
- combinational circuits
- sequential circuits
- latches
- flip-flops
Q4 | How many types of sequential circuits are?
- 2
- 3
- 4
- 5
Q5 | The sequential circuit is also called
- flip-flop
- latch
- strobe
- adder
Q6 | The basic latch consists of
- two inverters
- two comparators
- two amplifiers
- two adders
Q7 | In S-R flip-flop, if Q = 0 the output is said to be
- set
- reset
- previous state
- current state
Q8 | The output of latches will remain in set/reset untill
- the trigger pulse is given to change the state
- any pulse given to go into previous state
- they don’t get any pulse more
- the pulse is edge-triggered
Q9 | What is a trigger pulse?
- a pulse that starts a cycle of operation
- a pulse that reverses the cycle of operation
- a pulse that prevents a cycle of operation
- a pulse that enhances a cycle of operation
Q10 | A latch is an example of a
- monostable multivibrator
- astable multivibrator
- bistable multivibrator
- 555 timer
Q11 | Latch is a device with
- one stable state
- two stable state
- three stable state
- infinite stable states
Q12 | Why latches are called a memory devices?
- it has capability to stare 8 bits of data
- it has internal memory of 4 bit
- it can store one bit of data
- it can store infinite amount of data
Q13 | Two stable states of latches are
- astable & monostable
- low input & high output
- high output & low output
- low output & high input
Q14 | How many types of latches are __
- 4
- 3
- 2
- 5
Q15 | The full form of SR is
- system rated
- set reset
- set ready
- set rated
Q16 | The SR latch consists of
- 1 input
- 2 inputs
- 3 inputs
- 4 inputs
Q17 | The outputs of SR latch are
- x and y
- a and b
- s and r
- q and q’
Q18 | The first step of analysis procedure of SR latch is to
- label inputs
- label outputs
- label states
- label tables
Q19 | The inputs of SR latch are
- x and y
- a and b
- s and r
- j and k
Q20 | When a high is applied to the Set line of an SR latch, then
- q output goes high
- q’ output goes high
- q output goes low
- both q and q’ go high
Q21 | When both inputs of SR latches are low, the latch
- q output goes high
- q’ output goes high
- it remains in its previously set or reset state
- it goes to its next set or reset state
Q22 | When both inputs of SR latches are high, the latch goes
- unstable
- stable
- metastable
- bistable
Q23 | The full form of MOS is
- metal oxide semiconductor
- metal oxygen semiconductor
- metallic oxide semiconductor
- metallic oxygen semiconductor
Q24 | What are the types of MOSFET devices available?
- p-type enhancement type mosfet
- n-type enhancement type mosfet
- depletion type mosfet
- all of the mentioned
Q25 | Which insulating layer used in the fabrication of MOSFET?
- aluminium oxide
- silicon nitride
- silicon dioxide
- aluminium nitrate