Digital Logic Circuits Set 6

Computer Science Engineering (CSE)

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This set of Digital Logic Circuits DLC Multiple Choice Questions & Answers (MCQs) focuses on Digital Logic Circuits Set 6

Q1 | A technique used to reduce the magnitude of threshold voltage of MOSFET is the
  • use of complementary mosfet
  • use of silicon nitride
  • using thin film technology
  • increasing potential of the channel
Answer: use of silicon nitride
Q2 | What is used to higher the speed of operation in MOSFET fabrication?
  • ceramic gate
  • silicon dioxide
  • silicon nitride
  • poly silicon gate
Answer: poly silicon gate
Q3 | Why MOSFET is preferred over BJT in IC components?
  • mosfet has low packing density
  • mosfet has medium packing density
  • mosfet has high packing density
  • mosfet has no packing density
Answer: mosfet has low packing density
Q4 | Critical defects per unit chip area is for a MOS transistor.
  • high
  • low
  • neutral
  • very high
Answer: low
Q5 | MOS is being used in                        
  • lsi
  • vlsi
  • msi
  • both lsi and vlsi
Answer: both lsi and vlsi
Q6 | The D flip-flop has input.
  • 1
  • 2
  • 3
  • 4
Answer: 1
Q7 | The D flip-flop has output/outputs.
  • 2
  • 3
  • 4
  • 1
Answer: 2
Q8 | A D flip-flop can be constructed from an _ flip-flop.
  • s-r
  • j-k
  • t
  • s-k
Answer: s-r
Q9 | In D flip-flop, if clock input is HIGH & D=1, then output is                        
  • 0
  • 1
  • forbidden
  • toggle
Answer: 0
Q10 | Which of the following is correct for a gated D flip-flop?
  • the output toggles if one of the inputs is held high
  • only one of the inputs can be high at a time
  • the output complement follows the input when enabled
  • q output follows the input d when the enable is high
Answer: q output follows the input d when the enable is high
Q11 | With regard to a D latch                  
  • the q output follows the d input when en is low
  • the q output is opposite the d input when en is low
  • the q output follows the d input when en is high
  • the q output is high regardless of en’s input state
Answer: the q output follows the d input when en is high
Q12 | Which of the following is correct for a D latch?
  • the output toggles if one of the inputs is held high
  • q output follows the input d when the enable is high
  • only one of the inputs can be high at a time
  • the output complement follows the input when enabled
Answer: q output follows the input d when the enable is high
Q13 | Which of the following describes the operation of a positive edge-triggered D flip-flop?
  • if both inputs are high, the output will toggle
  • the output will follow the input on the leading edge of the clock
  • when both inputs are low, an invalid state exists
  • the input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock
Answer: the output will follow the input on the leading edge of the clock
Q14 | A positive edge-triggered D flip-flop will store a 1 when                  
  • the d input is high and the clock transitions from high to low
  • the d input is high and the clock transitions from low to high
  • the d input is high and the clock is low
  • the d input is high and the clock is high
Answer: the d input is high and the clock transitions from low to high
Q15 | Why do the D flip-flops receive its designation or nomenclature as ‘Data Flip-flops’?
  • due to its capability to receive data from flip-flop
  • due to its capability to store data in flip-flop
  • due to its capability to transfer the data into flip-flop
  • due to erasing the data from the flip-flop
Answer: due to its capability to transfer the data into flip-flop
Q16 | The characteristic equation of D-flip-flop implies that                        
  • the next state is dependent on previous state
  • the next state is dependent on present state
  • the next state is independent of previous state
  • the next state is independent of present state
Answer: the next state is independent of present state
Q17 | The asynchronous input can be used to set the flip-flop to the                          
  • 1 state
  • 0 state
  • either 1 or 0 state
  • forbidden state
Answer: either 1 or 0 state
Q18 | Input clock of RS flip-flop is given to                          
  • input
  • pulser
  • output
  • master slave flip-flop
Answer: pulser
Q19 | D flip-flop is a circuit having                          
  • 2 nand gates
  • 3 nand gates
  • 4 nand gates
  • 5 nand gates
Answer: 4 nand gates
Q20 | At the end of the clock pulse the value of output Q is uncertain. The situation is referred to as?
  • conversion condition
  • race around condition
  • lock out state
  • forbidden state
Answer: race around condition
Q21 | Master slave flip flop is also referred to as?
  • level triggered flip flop
  • pulse triggered flip flop
  • edge triggered flip flop
  • edge-level triggered flip flop
Answer: pulse triggered flip flop
Q22 | In a positive edge triggered JK flip flop, a low J and low K produces?
  • high state
  • low state
  • toggle state
  • no change state
Answer: no change state
Q23 | If one wants to design a binary counter, the preferred type of flip-flop is                          
  • d type
  • s-r type
  • latch
  • j-k type
Answer: j-k type
Q24 | S-R type flip-flop can be converted into D type flip-flop if S is connected to R through
  • or gate
  • and gate
  • inverter
  • full adder
Answer: inverter
Q25 | Which of the following flip-flops is free from the race around the problem?
  • t flip-flop
  • sr flip-flop
  • master-slave flip-flop
  • d flip-flop
Answer: t flip-flop
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