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This set of Digital Logic Circuits DLC Multiple Choice Questions & Answers (MCQs) focuses on Digital Logic Circuits Set 10
Q1 | UP-DOWN counter is also known as
- dual counter
- multi counter
- multimode counter
- two counter
Q2 | In an UP-counter, each flip-flop is triggered by
- the output of the next flip-flop
- the normal output of the preceding flip-flop
- the clock pulse of the previous flip-flop
- the inverted output of the preceding flip-flop
Q3 | In DOWN-counter, each flip-flop is triggered by
- the output of the next flip-flop
- the normal output of the preceding flip-flop
- the clock pulse of the previous flip-flop
- the inverted output of the preceding flip-flop
Q4 | Binary counter that count incrementally and decrement is called
- up-down counter
- lsi counters
- down counter
- up counter
Q5 | Once an up-/down-counter begins its count sequence, it
- starts counting
- can be reversed
- can’t be reversed
- can be altered
Q6 | In 4-bit up-down counter, how many flip-flops are required?
- 2
- 3
- 4
- 5
Q7 | A modulus-10 counter must have _
- 10 flip-flops
- 4 flip-flops
- 2 flip-flops
- synchronous clocking
Q8 | Which is not an example of a truncated modulus?
- 8
- 9
- 11
- 15
Q9 | The designation means that the
- up count is active-high, the down count is active-low
- up count is active-low, the down count is active-high
- up and down counts are both active-low
- up and down counts are both active-high
Q10 | The full form of SIPO is
- serial-in parallel-out
- parallel-in serial-out
- serial-in serial-out
- serial-in peripheral-out
Q11 | How can parallel data be taken out of a shift register simultaneously?
- use the q output of the first ff
- use the q output of the last ff
- tie all of the q outputs together
- use the q output of each ff
Q12 | What is meant by parallel load of a shift register?
- all ffs are preset with data
- each ff is loaded with data, one at a time
- parallel shifting of data
- all ffs are set with data
Q13 | After three clock pulses, the register contains
- 01110
- 00001
- 00101
- 00110
Q14 | What will be the 4-bit pattern after the second clock pulse? (Right-most bit first)
- 1100
- 0011
- 0000
- 1111
Q15 | In digital logic, a counter is a device which
- counts the number of outputs
- stores the number of times a particular event or process has occurred
- stores the number of times a clock pulse rises and falls
- counts the number of inputs
Q16 | A counter circuit is usually constructed of
- a number of latches connected in cascade form
- a number of nand gates connected in cascade form
- a number of flip-flops connected in cascade
- a number of nor gates connected in cascade form
Q17 | How many types of the counter are there?
- 2
- 3
- 4
- 5
Q18 | A decimal counter has states.
- 5
- 10
- 15
- 20
Q19 | Ripple counters are also called
- ssi counters
- asynchronous counters
- synchronous counters
- vlsi counters
Q20 | Synchronous counter is a type of
- ssi counters
- lsi counters
- msi counters
- vlsi counters
Q21 | Three decade counter would have
- 2 bcd counters
- 3 bcd counters
- 4 bcd counters
- 5 bcd counters
Q22 | BCD counter is also known as
- parallel counter
- decade counter
- synchronous counter
- vlsi counter
Q23 | The parallel outputs of a counter circuit represent the
- parallel data word
- clock frequency
- counter modulus
- clock count
Q24 | The time from the beginning of a read cycle to the end of tACS/tAA is called as
- write enable time
- data hold
- read cycle time
- access time
Q25 | Why did PROM introduced?
- to increase the storage capacity
- to increase the address locations
- to provide flexibility
- to reduce the size