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This set of Digital Logic Circuits DLC Multiple Choice Questions & Answers (MCQs) focuses on Digital Logic Circuits Set 4
Q1 | Standard TTL circuits operate with a volt power supply.
- 2
- 4
- 5
- 3
Q2 | A TTL gate may operate inadvertently as an
- digital amplifier
- analog amplifier
- inverter
- regulator
Q3 | Which statement below best describes a Karnaugh map?
- it is simply a rearranged truth table
- the karnaugh map eliminates the need for using nand and nor gates
- variable complements can be eliminated by using karnaugh maps
- a karnaugh map can be used to replace boolean rules
Q4 | Which of the examples below expresses the commutative law of multiplication?
- a + b = b + a
- a • b = b + a
- a • (b • c) = (a • b) • c
- a • b = b • a
Q5 | The Boolean expression Y = (AB)’ is logically equivalent to what single gate?
- nand
- nor
- and
- or
Q6 | The systematic reduction of logic circuits is accomplished by:
- symbolic reduction
- ttl logic
- using boolean algebra
- using a truth table
Q7 | Each “1” entry in a K-map square represents:
- a high for each input truth table condition that produces a high output
- a high output on the truth table for all low input combinations
- a low output for all possible high input conditions
- a don’t care condition for all possible input truth table combinations
Q8 | Each “0” entry in a K-map square represents:
- a high for each input truth table condition that produces a high output
- a high output on the truth table for all low input combinations
- a low output for all possible high input conditions
- a don’t care condition for all possible input truth table combinations
Q9 | Looping on a K-map always results in the elimination of
- variables within the loop that appear only in their complemented form
- variables that remain unchanged within the loop
- variables within the loop that appear in both complemented and uncomplemented form
- variables within the loop that appear only in their uncomplemented form
Q10 | Which of the following expressions is in the sum-of-products form?
- (a + b)(c + d)
- (a * b)(c * d)
- a* b *(cd)
- a * b + c * d
Q11 | What is an ambiguous condition in a NAND based S’-R’ latch?
- s’=0, r’=1
- s’=1, r’=0
- s’=1, r’=1
- s’=0, r’=0
Q12 | In a NAND based S’-R’ latch, if S’=1 & R’=1 then the state of the latch is
- no change
- set
- reset
- forbidden
Q13 | A NAND based S’-R’ latch can be converted into S-R latch by placing
- a d latch at each of its input
- an inverter at each of its input
- it can never be converted
- both a d latch and an inverter at its input
Q14 | The difference between a flip-flop & latch is
- both are same
- flip-flop consist of an extra output
- latches has one input but flip-flop has two
- latch has two inputs but flip-flop has one
Q15 | How many types of flip-flops are?
- 2
- 3
- 4
- 5
Q16 | The S-R flip flop consist of
- 4 and gates
- two additional and gates
- an additional clock input
- 3 and gates
Q17 | What is one disadvantage of an S-R flip-flop?
- it has no enable input
- it has a race condition
- it has no clock input
- invalid state
Q18 | One example of the use of an S-R flip-flop is as
- racer
- stable oscillator
- binary storage register
- transition pulse generator
Q19 | When is a flip-flop said to be transparent?
- when the q output is opposite the input
- when the q output follows the input
- when you can see through the ic packaging
- when the q output is complementary of the input
Q20 | On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when
- the clock pulse is low
- the clock pulse is high
- the clock pulse transitions from low to high
- the clock pulse transitions from high to low
Q21 | What is the hold condition of a flip-flop?
- both s and r inputs activated
- no active s or r input
- only s is active
- only r is active
Q22 | One example of the use of an S-R flip-flop is as
- transition pulse generator
- racer
- switch debouncer
- astable oscillator
Q23 | The truth table for an S-R flip-flop has how many VALID entries?
- 1
- 2
- 3
- 4
Q24 | When both inputs of a J-K flip-flop cycle, the output will
- be invalid
- change
- not change
- toggle
Q25 | Which of the following is correct for a gated D-type flip-flop?
- the q output is either set or reset as soon as the d input goes high or low
- the output complement follows the input when enabled
- only one of the inputs can be high at a time
- the output toggles if one of the inputs is held high