Digital Electronics And Logic Design Set 14 MCQs

Q1 | The inverter OR-gate and AND gate are called deeision-making elementsbecause they can recognize some input while disregarding others. A gate

words,high

bytes,low

bytes,high

character,low

Q2 | Which one of the following set of gates are best suited for 'parity' checking and 'parity' generation.

and, or, notgates

ex-nor orex-or gates

nand gates

norgates

Q3 | How many inputs are required for a 1-of-10 BCD decoder?

4

8

10

1

Q4 | Most demultiplexers facilitate which of the following?

decimal to hexadecimal

single input, multiple outputs

ac to dc

odd parity to even parity

Q5 | One application of a digital multiplexer is to facilitate:

code conversion

parity checking

parallel-to- serial data conversion

data generation

Q6 | Select one of the following statements that best describes the parity method of error detection:

best suited for detecting single-bit errors in transmitted codes.

best suited for detecting double-bit errors that occur during the transmission of codes from one location to another.

a and b

none of the above

Q7 | A multiplexed display:

accepts data inputs from one line and passes this data to multiple output lines

uses one display to present two or more pieces of information

accepts data inputs from multiple lines and passes this data to multiple output lines

accepts data inputs from several lines and multiplexe s this input data to four bcd lines

Q8 | In which of the following gates, the output is 1, if and only if at least one input is 1?

nor

and

or

nand

Q9 | The time required for a gate or inverter to change its state is called

rise time iz

decay time

propagation time

charging time

Q10 | The time required for a pulse to change from 10 to 90 percent of its maximum value is called

rise time iz

decay time

propagation time

operating speed

Q11 | The maximum frequency at which digital data can be applied to gate is called

operating speed

propagation speed

binary level transaction period

charging time

Q12 | What is the minimum number of two-input NAND gates used to perform the function of two input OR gate ?

one

two

three

four

Q13 | The time required for a pulse to decrease from 90 to 10 per cent of its maximum value is called

rise time

decay time

binary level transition period

propagatio n delay

Q14 | Which of the following gates would output 1 when one input is 1 and other input is 0 ?

or gate

and gate

nand gate

and gate

Q15 | Which of the following expressions is not equivalent to X ' ?

x nand x

x nor x

x nand 1

x nor 1

Q16 | Which of the following gates are added to the inputs of the OR gate to convert it to the NAND gate ?

not

and

or

xor

Q17 | The EXCLUSIVE NOR gate is equivalent to which gate followed by an inverter ?

or gate

and

nand

xor

Q18 | Which of the following gates is known as coincidence detector ?

and gate

or gate

not gate

nand gate

Q19 | Which table shows the logical state of a digital circuit output for every possible combination of logical states in the inputs ?

function table

truth table

routing table

ascii table

Q20 | A positive AND gate is also a negative

nand gate

nor gate

and gate

or gate

Q21 | An OR gate can be imagined as

switches connected in series

switches connected in parallel

mostransistors connected in series

none of these

Q22 | Which combination of gates does not allow the implementation of an arbitrary boolean function?

or gates and and gates only

or gates and exclusive or gate only

or gates and not gates only

nandgates only

Q23 | The output of NOR gate is

high if all of its inputs are high

low if all of its inputs are low

high if all of its inputs are low

high if only of its inputs is low

Q24 | A toggle operation cannot be performed using a single

nor gate

and gate

nand gate

xor gate

Q25 | Which table shows the electrical state of a digital circuit's output for every possible combination of electrical states in the inputs ?

function table

truth table

routing table

ascii table