Digital Electronics And Logic Design Set 8
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This set of Digital Electronics and Logic Design Multiple Choice Questions & Answers (MCQs) focuses on Digital Electronics And Logic Design Set 8
Q1 | If the channel is initially doped lightly with p-type impurity a conducting
- depletion
- enhancemen
- both mode
- none of
Q2 | If the region beneath the gate is left initially uncharged the gate field must induce achannel before current can flow. Thus the gate voltage enhances thechannel current and sucha device is said to operate in the
- depletion mode operation mos
- enhancemen t mode operation ofmos
- both mode
- none of this
Q3 | The n- channel MOS conducts when its
- gate- to- source voltage
- gate- to- source
- gate- to- source
- none of this
Q4 | The p- channel MOS conducts when its
- gate- to-
- gate- to-
- gate- to-
- none of
Q5 | The fan-out of a MOS-logic gate is higher than that of TTL gates because of its
- low input impedance
- high input impedance
- low output impedance
- high output impedance
Q6 | Which factor does not affect CMOS loading?
- charging time associated
- discharging time
- output capacitance
- input capacitanc
Q7 | Logic gates are the basic elements that make a
- analog system
- basic system
- gating system
- digital system
Q8 | Which of the following gate is a two-level logic gate
- or gate
- nand gate
- exclusiveor gate
- not
Q9 | Among the logic families, the family which can be used at very high frequency greater than 100 MHz in a 4 bit
- ttlas
- cmos
- ecl
- ttlls
Q10 | The fan Out of a 7400 NAND gate is
- 2ttl
- 5ttl
- 8ttl
- 10ttl
Q11 | Which transistor element is used in CMOS logic?
- fet
- mosfet
- bipolar
- unijunctio n
Q12 | CMOS circuits are extensively used for ON-chip computers mainly because of their extremely
- low power dissipation.
- high noise immunity.
- large packing density.
- low cost.
Q13 | Which equation is correct?
- vnl =vil(max) + vol(max)
- vnh =voh(min) + vih(min)
- vnl =voh(min) – vih(min)
- vnh =voh(min)–vih(min)
Q14 | The greater the propagation delay, the
- lower the maximum frequency
- higher the maximum frequency
- maximum frequency is unaffected
- minimum frequency is unaffected
Q15 | For a CMOS gate, which is the best speed-power product?
- 1.4 pj
- 1.6 pj
- 2.4 pj
- 3.3 pj
Q16 | In a TTL circuit, if an excessive number of load gate inputs are connected,
- voh(min) drops below voh
- voh drops below voh(min)
- voh exceeds voh(min)
- voh and voh(min) are unaffected
Q17 | Which is not a MOSFET terminal?
- gate
- drain
- source
- base
Q18 | An open-drain gate is the CMOS counterpart of
- an open- collector ttl gate
- a tristate ttl gate
- a bipolar junction transistor
- an emitter- coupled logic gate
Q19 | The active switching element used in all TTL circuits is the
- bipolar junction transistor (bjt
- field-effect transistor (fet
- metal-oxide semiconduct or field- effect transistor (mosfet
- unijunctio n transistor (uj)
Q20 | One output structure of a TTL gate is often referred to as a
- diode
- jbtarrangement
- totem-pole arrangement
- base, emitter, collector arrangeme nt
Q21 | An open-collector output requires
- a pull-down resistor
- a pull-up resistor
- no output resistor
- an output resistor
Q22 | Which is not an output state for tristate logic?
- high
- low
- high-z
- low-z
Q23 | TTL is alive and well, particularly in
- industrial applications
- millitary applications
- educational applications
- commercia lapplicatio ns
Q24 | A TTL NAND gate with IIL(max) of –1.6 mA per input drives eight TTL inputs. How much current does the drive output sink?
- –12.8 ma
- –8 ma
- –1.6 ma
- –25.6 ma
Q25 | A standard TTL circuit with a totem-pole output can sink, in the LOW state (IOL(max)),
- 16 ma
- 20 ma
- 24 ma
- 28ma