Digital Electronics And Logic Design Set 21
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This set of Digital Electronics and Logic Design Multiple Choice Questions & Answers (MCQs) focuses on Digital Electronics And Logic Design Set 21
Q1 | Which of the following flip-flop is free from race-around problem ?
- q flip-flop
- t flip-flop
- sr flip-flop
- master- slave jk flip-flop
Q2 | If the input J is connected through K input of J-K, then flip-flop will behave as a
- d type flip-flop
- t type flip- flop
- s-r flip-flop
- master slave jk flip-flop
Q3 | If a clock with time period 'T' is used with n stage shift register, then output of final stage will be delayed by
- nt sec
- (n-1)t sec
- n/t sec
- (2n+1)tsec
Q4 | Register is a
- set of capacitor used to register input instructions in a digital computer
- set to paper tapes and cards put in a file
- temporary storage unit within the cpu having dedicated or general purpose use
- part of the main memory
Q5 | The number of flip-flops required in a decade counter is
- 3
- 4
- 8
- 10
Q6 | If in a shift resistor Q0 is fed back to input the resulting counter is
- twisted ring with n : 1 scale
- ring counter with n : 1 scale
- twisted ring with 2n : 1 scale
- ring counter with 2 n : 1 scale
Q7 | A 8-bit serial in / parallel out shift register contains the value “8”, clock signal(s) will be required to shift the value completely out of the register.
- 1
- 2
- 4
- 8
Q8 | In a sequential circuit the next state is determined by and
- state variable, current state
- current state, flip- flop output
- current state and external input
- input and clock signal applied
Q9 | The divide-by-60 counter in digital clock is implemented by using two cascading counters:
- mod-6, mod-10
- mod-50,mod-10
- mod-10,mod-50
- mod-50,mod-6
Q10 | In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained.
- true
- false
Q11 | The minimum time for which the input signal has to be maintained at the input of flip-flop is called of the flip-flop.
- set-up time
- hold time
- pulse interval time
- pulse stability time (pst)
Q12 | 74HC163 has two enable input pins which are and
- enp, ent
- eni, enc
- enp, enc
- ent, eni
Q13 | to change in one input variable
- clock skew
- condition
- hold delay
- wait
Q14 | The input overrides the input
- asynchronous, synchronous
- synchronous,asynchronou s
- preset input (pre), clear input (clr)
- clear input (clr),preset input (pre)
Q15 | A decade counter is .
- mod-3 counter
- mod-5 counter
- mod-8 counter
- mod-10 counter
Q16 | In asynchronous transmission when the transmission line is idle,
- it is set to logic low
- it is set to logic high
- remains in previous state
- state of transmissi on line is not used to start transmissi on
Q17 | A Nibble consists of bits
- 2
- 4
- 8
- 16
Q18 | The output of this circuit is always .
- 1
- 0
- a
- abar
Q19 | The voltage gain of the Inverting Amplifier is given by the relation
- vout / vin = - rf / ri
- vout / rf = - vin / ri
- rf / vin = - ri / vout
- rf / vin = ri / vout
Q20 | LUT is acronym for
- look up table
- local user terminal
- least upper time period
- none of given options
Q21 | The three fundamental gates are
- and, nand, xor
- or, and, nand
- not, nor, xor
- not, or, and
Q22 | Stack is an acronym for
- fifo memory
- lifomemory
- flash memory
- bust flash memory
Q23 | is one of the examples of synchronous inputs.
- j-k input
- en input
- preset input (pre)
- clear input (clr)
Q24 | occurs when the same clock signal arrives at different times at different clock inputs due topropagation delay
- race condition
- clock skew
- ripple effect
- none of given options