Digital Electronics And Logic Design Set 17

Computer Science Engineering (CSE),

Electronics and Telecommunication Engineering [ENTC]

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This set of Digital Electronics and Logic Design Multiple Choice Questions & Answers (MCQs) focuses on Digital Electronics And Logic Design Set 17

Q1 | The 7447A is a BCD-to-7-segment decoder with ripple blanking input and output functions. The purpose of these lines is to .
  • turn off the display for any nonsignificant digit
  • turn off the display for any zero
  • turn off the display for leading or trailing zeros
  • test the display to assure all segments are operationa l
Answer: turn off the display for any nonsignificant digit
Q2 | One reason for using the sum-of-products form is that it can be implemented using all gates without much difficulty.
  • nor
  • nand
  • and
  • door
Answer: nand
Q3 | When an open occurs on the input of a CMOS gate, the output will .
  • go low, because there is no current in an open circuit
  • react as if the open input were a high
  • go high,since full voltage appears across an open
  • be unpredicta ble; it may go high or low
Answer: be unpredicta ble; it may go high or low
Q4 | To subtract a signed number (the subtrahend) from another signed number (the minuend) in the 2's complement system, the minuend is              .
  • complemented only if it is positive
  • complemente d only if it is negative
  • always complemente d
  • never compleme nted
Answer: never compleme nted
Q5 | In an odd-parity system, the data that will produce a parity bit = 1 is              .
  • data = 1010011
  • data = 1111000
  • data = 1100000
  • all of the above
Answer: all of the above
Q6 | The addition of two signed numbers in the 2's complement system can cause overflow. For overflow to occur both numbers must .
  • be positive
  • be negative
  • have the same sign
  • have opposite signs
Answer: have the same sign
Q7 | A Karnaugh map will .
  • eliminate the need for tedious boolean simplifications
  • allow any circuit to be implemented with just and and or gates
  • produce the simplest sum-of- products expression
  • give an overall picture of how the signals flow through the logic circuit
Answer: eliminate the need for tedious boolean simplifications
Q8 | An 8-bit binary number is input to an odd parity generator. The parity bit will equal 1 only if .
  • the number is odd
  • the number of 1s in the number is odd
  • the number is even
  • the number of 1s in the number is even
Answer: the number of 1s in the number is even
Q9 | Two 4-bit comparators are cascaded to form an 8-bit comparator. The cascading inputs of the most significant 4 bits should be connected.
  • to the outputs from the least significant 4- bit comparator
  • to the cascading inputs of the least significant 4- bit comparator
  • a = b to a logic high, a< b and a > b to a logic low
  • ground
Answer: to the outputs from the least significant 4- bit comparator
Q10 | When Karnaugh mapping, we must be sure to use the number of loops.
  • maximum
  • minimum
  • median
  • karnaugh
Answer: minimum
Q11 | The final output of a POS circuit is generated by .
  • an and
  • an or
  • a nor
  • a nand
Answer: an and
Q12 | After each circuit in a subsection of a VHDL program has been , they can be combined and the subsection can be tested.
  • designed
  • tested
  • engineered
  • produced
Answer: tested
Q13 | The series of IC's are pin, function, and voltage-level compatible with the 74 series IC's.
  • als
  • cmos
  • hct
  • 2n
Answer: hct
Q14 | The circuit produces a HIGH output whenever the two inputs are equal.
  • exclusive-and
  • exclusive- nand
  • exclusive- nor
  • exclusive- or
Answer: exclusive- nor
Q15 | A 4-bit adder has the following inputs: C0 = 0, A1 = 0, A2 = 1, A3 = 0, A4 = 1, B1 = 0, B2 = 1, B3 = 1, B4 = 1. The output will be .
  • 1100
  • 10101
  • 11000
  • 11
Answer: 11000
Q16 | The statement evaluates the variable status.
  • if/then
  • if/then/el se
  • case
  • elsif
Answer: if/then
Q17 | In VHDL, data can be each of the following types except .
  • bit
  • bit_vector
  • std_logic
  • std_vect or
Answer: std_vect or
Q18 | When grouping cells within a K-map, the cells must be combined in groups of .
  • 2\s
  • 1, 2, 4, 8, etc.
  • 4\s
  • 3\s
Answer: 1, 2, 4, 8, etc.
Q19 | The circuit produces a HIGH output whenever the two inputs are unequal.
  • exclusive-and
  • exclusive- nor
  • exclusive-or
  • inexclusive-or
Answer: exclusive-or
Q20 | Occasionally, a particular logic expression will be of no consequence in the operation of a circuit, such as in a BCD-to-decimal converter. These result in terms in the K-map and can be treated as either                 or , in order to the resulting term.
  • don\t care, 1\s, 0\s, simplify
  • spurious, and\s, or\s,eliminate
  • duplicate, 1\s, 0\s, verify
  • spurious, 1\s, 0\s,simplify
Answer: don\t care, 1\s, 0\s, simplify
Q21 | A good rule of thumb for determining the pin numbers of dual-in-line package IC chips would be to place the notch to your right and pin #1 will always be in the lower right corner.
  • true
  • false
  • none of the above
  • can not predict
Answer: false
Q22 | The carry output of each adder in a ripple adder provides an additional sum output bit.
  • true
  • false
  • none of the above
  • can not predict
Answer: true
Q23 | Truth tables are great for listing all possible combinations of independent variables.
  • true
  • false
  • none of the above
  • can not predict
Answer: true
Q24 | A square in the top row of a K-map is considered to be adjacent to its corresponding square in the bottom row.
  • true
  • false
  • none of the above
  • can not predict
Answer: true
Q25 | To implement the full-adder sum functions, two exclusive-OR gates can be used.
  • true
  • false
  • none of the above
  • can not predict
Answer: true
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