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This set of Digital Electronics and Logic Design Multiple Choice Questions & Answers (MCQs) focuses on Digital Electronics And Logic Design Set 19

Q1 | Which of the following is not a form of multivibrator?
  • astable.
  • monostable.
  • tristable.
  • bistable.
Q2 | A J-K flip-flop has two control inputs. What happens to the Q output on the active edge of the clock if both control inputs are asserted simultaneously?
  • the q output toggles to the other state.
  • the q output is set to 1.
  • the q output is reset to 0.
  • the q output remains unchanged.
Q3 | A master/slave bistable is formed using two bistable connected in series.
  • true
  • false
Q4 | An astable has two metastable states and produces the function of a digital oscillator
  • true
  • false
Q5 | In synchronous counters the clock input of each of the bistables are connected together so that each changes state at the same time.
  • true
  • false
Q6 | 1: When the maximum clock rate is quoted for a logic family, then it applies to a
  • shift register
  • flip-flop
  • counter
  • multiplexe r
Q7 | 2: The number of flip-flops required in a modulo N counter is
  • log2 (n) + 1
  • log2(n-1)
  • log2 (n)
  • n log2 (n)
Q8 | 3: Flip-flop outputs are always
  • complimentary
  • the same
  • independent of each other
  • same as previous input
Q9 | 4: How many gates (minimum) are needed for a 3-bit up-counter using standard binary and using T lip-lops ? Assume unlimited fan-in.
  • 6
  • 3
  • 2
  • 1
Q10 | 5: The clear data and present input of the JK lip-lop are known as
  • synchronous inputs
  • directed inputs
  • either (a) or (b)
  • none of thes
Q11 | A mod-2 counter followed by a mod-5 counter is
  • same as a mode-5 counter followed by a mod- 2 counter
  • a decade counter
  • a mod-7 counter
  • ripple carry counter
Q12 | What is the maximum counting speed of a 4-bit binary counter which is composed of flip-flops with a propagation delay of 25 ns ?
  • 1 mhz
  • 10 mhz
  • 100 mhz
  • 8 mhz
Q13 | 8: A JK flip-lop has its J input connected to logic level 1 and its input to the Q output. A clock pulse is fed to its clock input. The flip-lop will now
  • change its state at each clock pulse
  • go to state 1 and stay there
  • go to state 0 and stay there
  • retain its previous state
Q14 | 9: Consider an RS lip-lops with both inputs set to 0. If a momentary '1' is applied at the input S,then the output
  • q will flip from 0 to 1 and thenback to 0
  • q will flip from 0 to 1 and then back to 0
  • q will flip from 1 to 0
  • q will flip from 0 to 1
Q15 | The output of a sequential circuit depends on
  • present inputs only
  • past outputs only
  • both present and past inputs
  • present outputs only
Q16 | The ring counter is analogous to
  • toggle switch
  • latch
  • stepping switch
  • j-k flip- flop
Q17 | 12: In a digital counter circuit feedback loop is introduced to
  • improve distortion
  • improve stability
  • reduce the number of input pulses to reset the counter
  • asynchron ous input and output pulses
Q18 | A J-K lip-lop has its J-input connected to logic level 1 and its input to the Q output pulse is fed to its clock input the flip-flop will now
  • change its state at each clock pulse
  • go to state 1 and stay there
  • go to state 0 and stay there
  • retain its present state
Q19 | Which of the following conditions must be met to avoid race around problem ?
  • Δ t < tp < t
  • t > Δt > tp
  • 2 tp < Δt < t
  • none of these
Q20 | Match List I with List II and select the correct answer form the codes given below the list List IA. A shift register can beB. A multiplexerC. A decoder can List II 1.for parallel to serial conversion2.to generate memory can be used chip select 3.for parallel to serial conversionCODES: A B C
  • 3 1 2
  • 2 3 1
  • 1 3 2
  • 1 2 3
Q21 | With the use of an electronic counter six capsules are to be filled in bottles automatically. In such a counter what will be the number of flip- flops required ?
  • 3
  • 12
  • 6
  • 8
Q22 | A pulse train can be delayed by a finite number of clock periods using
  • a serial-in serial-out shift register
  • a serial-in parallel-out shift register
  • both (a) and (b)
  • a parallel- in parallel- out shift register
Q23 | How many illegitimate states has synchronous mod-6 counter ?
  • 3
  • 2
  • 1
  • 6
Q24 | A 2 bit binary multiplier can be implemented using
  • 2 input ands only
  • 2 input xorsand 4 input and gates only
  • 2 input nors and one xnor gate
  • nor gates and shift registers
Q25 | A ring counter is same as
  • up-down counter
  • parallel- counter
  • shift register
  • ripple carry counter