Digital Electronics And Logic Design Set 11 MCQs

Q1 | When is a level-shifter circuit needed in interfacing logic?

a level shifter is always needed.

a level shifter is never needed.

when the supply voltages are the same

when the supply voltages are different

Q2 | A TTL totem-pole circuit is designed so that the output transistors:

are always on together

provide linear phase splitting

provide voltage regulation

are never on together

Q3 | The most common TTL series ICs are:

e-mosfet

7400

quad

ac00

Q4 | Which family of devices has the characteristic of preventing saturation during operation?

ttl

ecl

mos

iil

Q5 | How many 74LSTTL logic gates can be driven from a 74TTL gate?

10

20

30

40

Q6 | What is the difference between the 74HC00 series and the 74HCT00 series of CMOS logic?

the hct series is faster.

the hct series is slower.

he hct series is input and output voltage compatible with ttl.

the hct series is not input and output voltagecompatible with ttl.

Q7 | Why are the maximum value of VOL and the minimum value of VOH used to determine the noise margin rather than the typical values for these parameters?

these are worst-case conditions.

these are normal conditions.

these are best-case conditions.

it doesn\t matter what values are used.

Q8 | What is the standard TTL noise margin?

5.0 v

0.0 v

0.8 v

0.4 v

Q9 | Which logic family is characterized by a multiemitter transistor on the input?

ecl

cmos

ttl

none of the above

Q10 | he problem of the VOH(min) of a TTL IC being too low to drive a CMOS circuit and meet the CMOS requirement of VIH(min) is usually easily overcome by:

adding a fixed voltage- divider bias resistive network at the output of the ttl device

avoiding this condition and only using ttl to drive ttl

adding an external pull- down resistor to ground

adding an external pull-up resistor to vcc

Q11 | How does the 4000 series of CMOS logic compare in terms of speed and power dissipation to the standard family of TTL logic?

more power dissipation and slower speed

more power dissipation and faster speed

less power dissipation and faster speed

less powerdissipation andslower speed

Q12 | What should be done with unused inputs to a TTL NAND gate?

let them float

tie them low

tie them high

none of the above

Q13 | Which of the following logic families has the highest maximum clock frequency?

s-ttl

as-ttl

hs-ttl

hcmos

Q14 | Why is the fan-out of CMOS gates frequency dependent?

each cmos input gate has a specific propagation time and this limits the number of different gates that can be connected to the output of a cmos gate.

when the frequency reaches the critical value, the gate will only be capable of delivering 70% of the normal output voltage andconsequently the output power will be one-half of normal; this defines the upper operating frequency.

the higher the number of gates attached to the output, the more frequently they will have to be serviced, thus reducing the frequency at which each will be serviced with an input signal.

the input gates of the fets are predomina ntly capacitive, and as the signal frequency increases the capacitive loading also increases, thereby limiting the number of loads that may be attached to the output of thedriving gate.

Q15 | What must be done to interface TTL to CMOS?

a dropping resistor must be used on the cmos 12 vsupply to reduce it to 5 v for the ttl.

as long as the cmos supply voltage is 5 v, they can be interfaced; however, the fan-out of the ttl is limited to five cmos gates.

a 5 v zener diode must be placed across the inputs of the ttl gates in order to protect them from the higher output voltages of the cmos gates.

a pull-up resistor must be used between the ttl output- cmosinput node and vcc; the value of rp will depend on the number of cmosgates connected to the node.

Q16 | What causes low-power Schottky TTL to use less power than the 74XX series TTL?

the schottky- clamped transistor

nothing. the 74xx series uses less power.

a larger value resistor

using nandgates

Q17 | What are the major differences between the 5400 and 7400 series of ICs?

the 5400series are military grade and require tighter supply voltages and temperatures.

the 5400series are military grade and allow for a wider range of supply voltages and temperature s.

the 7400series are an improvement over the original 5400s.

the 7400series was originally developed by texas instrumen ts. the 5400series was brought out by national semicondu ctors after ti\spatents expired, as a second supply source.

Q18 | Which of the following statements apply to CMOS devices?

the devices should not be inserted into circuits with the power on.

all tools, test equipment, and metal workbenches should be tied to earth ground.

the devices should be stored and shipped in antistatic tubes or conductive foam.

all of the above.

Q19 | Which of the logic families listed below allows the highest operating frequency?

74as

ecl

hcmos

54s

Q20 | What is the increase in switching speed between 74LS series TTL and 74HC/HCT (High-Speed CMOS)?

5

10

50

100

Q21 | What does ECL stand for?

electron- coupled logic;

emitter- coupled logic;

energy- coupled logic;

none of above

Q22 | What is unique about TTL devices such as the 74S00?

the gate transistors are silicon (s), and the gates therefore have lower values of leakage current.

the s denotes the fact that a single gate is present in the ic rather than the usual package of 2–6 gates.

the s denotes a slow version of the device, which is a consequence of its higherpower rating.

the devices use schottky transistors anddiodes to prevent them from going into saturation; this results in faster turn on and turn off times, which translates intohigher frequency operation.

Q23 | he bipolar TTL logic family that was developed to increase switching speed by preventing transistor saturation is:

emitter- coupled logic (ecl).

current- mode logic (cml).

transistor- transistor logic (ttl).

emitter- coupled logic (ecl) and transistor- transistor logic (ttl).

Q24 | In TTL the noise margin is between

0.4 v and 0.8 v.

0.0 v and 0.4 v.

0.0 v and 0.5 v.

0.0v and0.8 v.

Q25 | What is the transitive voltage for the voltage input of a CMOS operating from 10V supply

1v

5v

10v

15v