Digital Electronics Set 11
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This set of Digital Electronics Multiple Choice Questions & Answers (MCQs) focuses on Digital Electronics Set 11
Q1 | Non inverting dynamic register storage cell consists of transistors for nMOS and for CMOS.
- six, eight
- eight, six
- five, six
- six, five
Q2 | Register cell consists of
- inverter
- pass transistor
- inverter & pass transistor
- none of the mentioned
Q3 | In a four bit dynamic shift register basic nMOS transistor or inverters are connected in
- series
- cascade
- parallel
- series and parallel
Q4 | In four bit dynamic shift register output is obtained
- parallel output at inverters 1, 3, 5, 7
- parallel output at inverters 1, 5, 8
- parallel output at all inverters
- parallel output at inverter 2, 4, 6, 8
Q5 | Output values of Moore type FSM are determined by its
- input values
- output values
- clock input
- current state
Q6 | Moore machine output is synchronous.
- true
- false
Q7 | Finite state machines are combinational logic systems.
- true
- false
Q8 | What happens if the input is high in FSM?
- change of state
- no transition in state
- remains in a single state
- invalid state
Q9 | What happens if the input is low in FSM?
- change of state
- no transition in state
- remains in a single state
- invalid state
Q10 | In FSM diagram what does circle represent?
- change of state
- state
- output value
- initial state
Q11 | In the FSM diagram, what does arrow between the circles represent?
- change of state
- state
- output value
- initial state
Q12 | In the FSM diagram, what does the information below the line in the circle represent?
- change of state
- state
- output value
- initial state
Q13 | Moore machine has states than a mealy machine.
- fewer
- more
- equal
- negligible
Q14 | State transition happens in every clock cycle.
- once
- twice
- thrice
- four times
Q15 | In digital logic, a counter is a device which
- counts the number of outputs
- stores the number of times a particular event or process has occurred
- stores the number of times a clock pulse rises and falls
- counts the number of inputs
Q16 | A counter circuit is usually constructed of
- a number of latches connected in cascade form
- a number of nand gates connected in cascade form
- a number of flip-flops connected in cascade
- a number of nor gates connected in cascade form
Q17 | A decimal counter has states.
- 5
- 10
- 15
- 20
Q18 | What is the maximum possible range of bit-count specifically in n-bit binary counter consisting of ‘n’ number of flip-flops?
- 0 to 2n
- 0 to 2n + 1
- 0 to 2n – 1 d) 0 to 2n+1/2
Q19 | How many types of the counter are there?
- 2
- 3
- 4
- 5
Q20 | Three decade counter would have
- 2 bcd counters
- 3 bcd counters
- 4 bcd counters
- 5 bcd counters
Q21 | BCD counter is also known as
- parallel counter
- decade counter
- synchronous counter
- vlsi counter
Q22 | The parallel outputs of a counter circuit represent the
- parallel data word
- clock frequency
- counter modulus
- clock count
Q23 | Ring shift and Johnson counters are
- synchronous counters
- asynchronous counters
- true binary counters
- synchronous and true binary counters
Q24 | What is the difference between a shift-right register and a shift-left register?
- there is no difference
- the direction of the shift
- propagation delay
- the clock input
Q25 | What is a transceiver circuit?
- a buffer that transfers data from input to output
- a buffer that transfers data from output to input
- a buffer that can operate in both directions
- a buffer that can operate in one direction