Digital Electronics And Logic Design Set 24
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This set of Digital Electronics and Logic Design Multiple Choice Questions & Answers (MCQs) focuses on Digital Electronics And Logic Design Set 24
Q1 | Q2 :=Q1 OR X OR Q3The above ABEL expression will be
- q2:= q1 $ x $ q3
- q2:= q1 # x# q3
- q2:= q1 & x& q3
- q2:= q1 ! x ! q3
Q2 | Above is the circuit diagram of
- asynchronous up-counter
- asynchronou s down- counter
- synchronous up-counter
- synchrono us down- counter
Q3 | The high density FLASH memory cell is implemented using
- 1 floating-gate mos transistor
- 2 floating- gate mos transistors
- 4 floating- gate mos transistors
- 6 floating- gate mos transistors
Q4 | A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 iswaiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing .
- 1110
- 111
- 1000
- 1001
Q5 | At T0 the value stored in a 4-bit left shift was “1”. What will be the value of register after three clock pulses?
- 2
- 4
- 6
- 8
Q6 | A multiplexer with a register circuit converts
- serial data to parallel
- parallel data to serial
- serial data to serial
- parallel data to parallel
Q7 | In outputs depend only on the combination of current state and inputs
- mealy machine
- moore machine
- state reduction table
- state assignmen t table
Q8 | The input overrides the input
- asynchronous, synchronous
- synchronous,asynchronou s
- preset input (pre), clear input (clr)
- clear input (clr),preset input (pre)
Q9 | For a gated D-Latch if EN=1 and D=1 then Q(t+1) =
- 0
- 1
- q(t)
- invalid
Q10 | If S=1 and R=1, then Q(t+1) = for negative edge triggered flip- flop
- 0
- 1
- invalid
- input is invalid
Q11 | The sequence of states that are implemented by a n-bit Johnson counter is
- n+2
- 2n
- 2 raise to power n
- n raise to power 2
Q12 | The alternate solution for a multiplexer and a register circuit is
- parallel in / serial out shift register
- serial in / parallel out shift register
- parallel in / parallel out shift register
- serial in / serial out shift register
Q13 | THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A
- gated flip- flops
- pulse triggered flip-flops
- positive- edge triggered flip-flops
- negative-edge triggere d flip- flops
Q14 | Flip flops are also called
- bi-stable dualvibrators
- bi-stable transformer
- bi-stable multivibrator s
- bi-stable singlevibra tors
Q15 | A transparent mode means
- the changes in the data at the inputs of the latch are seen at the output
- the changes in the data at the inputs of the latch are not seen at the output
- propagation delay is zero (output is immediately changed when clock signal is applied)
- input hold time is zero (no need to maintain input after clocktransition)
Q16 | Given the state diagram of an up/down counter, we can find
- the next state of a given present state
- the previous state of a given present state
- both the next and previous states of a given state
- the state diagram shows only the inputs/out puts of a given states
Q17 | In Q output of the last flip-flop of the shift register is connected to the data input of the firstflip-flop of the shift register.
- moore machine
- meally machine
- johnson counter
- ring counter
Q18 | status.
- 3
- 7
- 8
- 15
Q19 | We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZand 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by
- using s-r flop- flop
- d-flipflop
- j-k flip-flop
- t-flip-flop
Q20 | If S=1 and R=1, then Q(t+1) = for negative edge triggered flip- flop
- 0
- 1
- invalid
- input is invalid
Q21 | WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO
- the flop- flop is triggered
- q=0 and q‟=1
- q=1 and q’=0
- the output of flip- flop remains unchang ed
Q22 | If an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0, the latch willbe
- set
- reset
- invalid
- clear
Q23 | For a positive edge-triggered J-K flip-flop with both J and K HIGH, the outputs will if the clock goes HIGH.
- toggle
- set
- reset
- not change
Q24 | What is the difference between a D latch and a D flip-flop?
- the d latch has a clock input.
- the d flip- flop has an enable input.
- the d latch is used for faster operation.
- the d flip- flop has a clock input.
Q25 | A frequency counter
- counts pulse width
- counts no. of clock pulses in 1 second
- counts high and low range of given clock pulse
- none of given options