Digital Electronics And Logic Design Set 23

Computer Science Engineering (CSE),

Electronics and Telecommunication Engineering [ENTC]

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This set of Digital Electronics and Logic Design Multiple Choice Questions & Answers (MCQs) focuses on Digital Electronics And Logic Design Set 23

Q1 | THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A                    
  • gated flip- flops
  • pulse triggered flip-flops
  • positive- edge triggered flip-flops
  • negative-edge triggere d flip- flops
Answer: negative-edge triggere d flip- flops
Q2 | A positive edge-triggered flip-flop changes its state when                             
  • low-to-high transition of clock
  • high-to-low transition of clock
  • enable input (en) is set
  • preset input (pre) isset
Answer: low-to-high transition of clock
Q3 | Flip flops are also called                        
  • bi-stable dualvibrators
  • bi-stable transformer
  • bi-stable multivibrator s
  • bi-stable singlevibra tors
Answer: bi-stable multivibrator s
Q4 | A FIELD-PROGRAMMABLE LOGIC ARRAY CAN BE PROGRAMMED BY THE USER AND NOT BYTHE MANUFACTURER.
  • true
  • false
Answer: true
Q5 | THE FOUR OUTPUTS OF TWO 4-INPUT MULTIPLEXERS, CONNECTED TO FORM A 16-INPUTMULTIPLEXER, ARE CONNECTED TOGETHER THROUGH A 4-INPUT                  GATE
  • and
  • or
  • nand
  • xor
Answer: or
Q6 | A particular half adder has
  • 2 inputs and1 output
  • 2 inputsand 2 output
  • 3 inputsand 1 output
  • 3 inputsand 2 output
Answer: 2 inputsand 2 output
Q7 | A full-adder has a Cin = 0. What are the sum ( ) and the carry (Cout)when A = 1 and B = 1?
  • 0
  • 0
  • = 1, cout = 0
  • = 1, cout= 1
Answer: 0
Q8 | The sequence of states that are implemented by a n-bit Johnson counter is
  • n+2 (n plus 2)
  • 2n (n multiplied by 2)
  • 2n (2 raise to power n)
  • n2 (n raise to power 2)
Answer: 2n (n multiplied by 2)
Q9 | A GAL is essentially a .
  • non- reprogrammab le pal
  • pal that is programmed only by the manufacture r
  • very large pal
  • reprogra mmable pal
Answer: reprogra mmable pal
Q10 | The alternate solution for a demultiplexer-register combination circuit is                
  • parallel in / serial out shift register
  • serial in / parallel out shift register
  • parallel in / parallel out shift register
  • serial in / serial out shift register
Answer: serial in / parallel out shift register
Q11 | A transparent mode means                      
  • the changes in the data at the inputs of the latch are seen at the output
  • the changes in the data at the inputs of the latch are not seen at the output
  • propagation delay is zero (output is immediately changed when clock signal is applied)
  • input hold time is zero (no need to maintain input after clocktransition)
Answer: the changes in the data at the inputs of the latch are seen at the output
Q12 |                  occurs when the same clock signal arrives at different times at different clock inputs due topropagation delay.
  • race condition
  • clock skew
  • ripple effect
  • none of given options
Answer: clock skew
Q13 |                     is one of the examples of asynchronous inputs.
  • j-k input
  • s-r input
  • d input
  • clear input (clr)
Answer: clear input (clr)
Q14 | Bi-stable devices remain in either of their states unless the inputs force the device to switch its state
  • ten
  • eight
  • three
  • two
Answer: two
Q15 | RCO Stands for                 
  • reconfiguratio n counter output
  • reconfigurati on clock output
  • ripple counter output
  • ripple clock output
Answer: ripple clock output
Q16 | A positive edge-triggered flip-flop changes its state when                             
  • low-to-high transition of clock
  • high-to-low transition of clock
  • enable input (en) is set
  • preset input (pre) isset
Answer: low-to-high transition of clock
Q17 | The low to high or high to low transition of the clock is considered to be a(n)                
  • state
  • edge
  • trigger
  • one-shot
Answer: edge
Q18 | In asynchronous digital systems all the circuits change their state with respect to a common clock
  • true
  • false
Answer: false
Q19 | If the S and R inputs of the gated S-R latch are connected together using a gate then there is only asingle input to the latch. The input is represented by D instead of S or R (A gated D-Latch)
  • and
  • or
  • not
  • xor
Answer: not
Q20 | If S=1 and R=0, then Q(t+1) = for positive edge triggered flip-flop
  • 0
  • 1
  • invalid
  • input is invalid
Answer: 1
Q21 | 3-to-8 decoder can be used to implement Standard SOP and POS Boolean expressions
  • true
  • false
Answer: true
Q22 | The Encoder is used as a keypad encoder.
  • 2-to-8 encoder
  • 4-to-16encoder
  • bcd-to-decimal
  • decimal- to-bcd priority
Answer: decimal- to-bcd priority
Q23 | The simplest and most commonly used Decoders are the Decoders
  • n to 2n
  • (n-1) to 2n
  • (n-1) to (2n- 1)
  • n to 2n-1
Answer: n to 2n
Q24 | A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and theresulting output of each value.
  • true
  • false
Answer: true
Q25 | The decimal “17” in BCD will be represented as 10001(right opt is not given)
  • 11101
  • 11011
  • 10111
  • 11110
Answer: 10111
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