Digital Electronics And Logic Design Set 22

Computer Science Engineering (CSE),

Electronics and Telecommunication Engineering [ENTC]

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This set of Digital Electronics and Logic Design Multiple Choice Questions & Answers (MCQs) focuses on Digital Electronics And Logic Design Set 22

Q1 | Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the counter countsupward (0000 to 1111) and if external input (X) is “1” the counter counts downward (1111 to 0000), nowsuppose that the present state is “1100” and X=1, the next state of the counter will be                     
  • 0
  • 1101
  • 1011
  • 1111
Answer: 1101
Q2 | In a state diagram, the transition from a current state to the next state is determined by
  • current state and the inputs
  • current state and outputs
  • previous state and inputs
  • previous state and outputs
Answer: current state and the inputs
Q3 |                is used to simplify the circuit that determines the next state.
  • state diagram
  • next state table
  • state reduction
  • state assignmen t
Answer: state assignmen t
Q4 | The diagram given below represents                   
  • demorgans law
  • associative law
  • product of sum form
  • sum of product form
Answer: sum of product form
Q5 | The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop                     
  • doesn’t have an invalid state
  • sets to clear when both j= 0 and k = 0
  • it does not show transition on change in pulse
  • it does not accept asynchron ous inputs
Answer: doesn’t have an invalid state
Q6 | A multiplexer with a register circuit converts                 
  • serial data to parallel
  • parallel data to serial
  • serial data to serial
  • parallel data to parallel
Answer: parallel data to serial
Q7 | A GAL is essentially a .
  • non- reprogrammab le pal
  • pal that is programmed only by the manufacture r
  • very large pal
  • reprogra mmable pal
Answer: reprogra mmable pal
Q8 | in , all the columns in the same row are either read or written.
  • sequential access
  • mos access
  • fast mode page access
  • none of given options
Answer: fast mode page access
Q9 | How many flip-flops are required to produce a divide-by-32 device?
  • 2
  • 5
  • 6
  • 4
Answer: 5
Q10 | A reduced state table has 18 rows. The minimum number of flip flops needed to implement the sequential machine is
  • 18
  • 9
  • 5
  • 4
Answer: 5
Q11 | Advantage of synchronous sequential circuits over asynchronous ones is
  • faster operation
  • ease of avoiding problems due to hazard
  • lower hardware requirement
  • better noise immunity
Answer: faster operation
Q12 | The characteristic equation of a JK flip flop is
  • qn+1=j.qn+k.qn
  • qn+1=j.q’n+ k’.qn
  • qn+1=qnj.k
  • qn+1=(j+k)qn
Answer: qn+1=j.q’n+ k’.qn
Q13 | WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO -------
  • the flop- flop is triggered
  • q=0 and q‟=1
  • q=1 and q‟=0
  • the output of flip- flop remains unchang ed
Answer: the output of flip- flop remains unchang ed
Q14 | In Q output of the last flip-flop of the shift register is connected to the data input of the firstflip-flop of the shift register.
  • moore machine
  • meally machine
  • johnson counter
  • ring counter
Answer: ring counter
Q15 | 5-BIT JOHNSON COUNTER SEQUENCES THROUGH STATES
  • 7
  • 10
  • 32
  • 25
Answer: 10
Q16 | A 8-bit serial in / parallel out shift register contains the value “8”,           clock signal(s) will be required to shiftthe value completely out of the register.
  • 1
  • 2
  • 4
  • 8
Answer: 8
Q17 | AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS “1”. WHAT WILL BE THE VALUE OFREGISTER AFTER THREE CLOCK PULSES?
  • 2
  • 4
  • 6
  • 8
Answer: 8
Q18 | The alternate solution for a multiplexer and a register circuit is                 
  • parallel in / serial out shift register
  • serial in / parallel out shift register
  • parallel in / parallel out shift register
  • serial in / serial out shift register
Answer: parallel in / serial out shift register
Q19 | A multiplexer with a register circuit converts                 
  • serial data to parallel
  • parallel data to serial
  • serial data to serial
  • parallel data to parallel
Answer: parallel data to serial
Q20 | A synchronous decade counter will have flip-flops
  • 3
  • 4
  • 7
  • 10
Answer: 4
Q21 | In outputs depend only on the current state.
  • mealy machine
  • moore machine
  • state reduction table
  • state assignmen t table
Answer: moore machine
Q22 | Given the state diagram of an up/down counter, we can find                
  • the next state of a given present state
  • the previous state of a given present state
  • both the next and previous states of a given state
  • the state diagram shows only the inputs/out puts of a given states
Answer: the next state of a given present state
Q23 | THE HOURS COUNTER IS IMPLEMENTED USING                   
  • only a single mod- 12 counter is required
  • mod-10 and mod-6 counters
  • mod-10 and mod-2 counters
  • a single decade counter and a flip-flop
Answer: a single decade counter and a flip-flop
Q24 | The design and implementation of synchronous counters start from
  • truth table
  • k-map
  • state table
  • state diagram
Answer: state diagram
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