Digital Electronics And Logic Design Set 16

Computer Science Engineering (CSE),

Electronics and Telecommunication Engineering [ENTC]

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This set of Digital Electronics and Logic Design Multiple Choice Questions & Answers (MCQs) focuses on Digital Electronics And Logic Design Set 16

Q1 | What is the indication of a short on the input of a load gate?
  • only the output of the defective gate is affected.
  • there is a signal loss to all gates on the node.
  • the affected node will be stuck in the low state.
  • there is a signal loss to all gates on the node, and the affected node will be stuck in thelow state.
Answer: there is a signal loss to all gates on the node, and the affected node will be stuck in thelow state.
Q2 | In HDL, LITERALS is/are:
  • digital systems.
  • scalars.
  • binary coded decimals.
  • a numbering system.
Answer: scalars.
Q3 | Which of the following expressions is in the sum-of-products form?
  • (a + b )(c + d )
  • (ab )(cd )
  • ab (cd )
  • ab + cd
Answer: ab + cd
Q4 | The carry propagation can be expressed as .
  • cp = ab
  • cp = a + b
Answer: cp = a + b
Q5 | A decoder can be used as a demultiplexer by .
  • tying all enable pins low
  • tying all data-select lines low
  • tying all data- select lines high
  • using the input lines for data selection and an enable line for data input
Answer: using the input lines for data selection and an enable line for data input
Q6 | How many 4-bit parallel adders would be required to add two binary numbers each representing decimal numbers up through 30010?
  • 1
  • 2
  • 3
  • 4
Answer: 3
Q7 | Which statement below best describes a Karnaugh map?
  • a karnaugh map can be used to replace boolean rules.
  • the karnaugh map eliminates the need for using nand and nor gates.
  • variable complements can be eliminated by using karnaugh maps.
  • karnaugh maps provide a visual approach to simplifyin g boolean expression s.
Answer: karnaugh maps provide a visual approach to simplifyin g boolean expression s.
Q8 | A certain BCD-to-decimal decoder has active-HIGH inputs and active- LOW outputs. Which output goes LOW when the inputs are 1001?
  • 0
  • 3
  • 9
  • none. all outputs are high.
Answer: 9
Q9 | A full-adder has a Cin = 0. What are the sum and the carry (Cout) when A= 1 and B = 1?
  • 0
  • 0
  • 0
  • 0
Answer: 0
Q10 | When adding an even parity bit to the code 110010, the result is .
  • 1110010
  • 110010
  • 1111001
  • 1101
Answer: 1110010
Q11 | Which of the following combinations of logic gates can decode binary 1101?
  • one 4-input and gate
  • one 4-input and gate, one or gate
  • one 4-input nand gate, one inverter
  • one 4- input and gate, one inverter
Answer: one 4- input and gate, one inverter
Q12 | What is the indication of a short to ground in the output of a driving gate?
  • only the output of the defective gate is affected.
  • there is a signal loss to all load gates.
  • the node may be stuck in either the high or the low state.
  • the affected node will be stuck in the highstate.
Answer: there is a signal loss to all load gates.
Q13 | How many outputs would two 8-line-to-3-line encoders, expanded to a 16-line-to-4-line encoder, have?
  • 3
  • 4
  • 5
  • 6
Answer: 4
Q14 | A half-adder does not have .
  • carry in
  • carry out
  • two inputs
  • all of the above
Answer: carry in
Q15 | A circuit that can convert one of ten numerical keys pressed on a keyboard to BCD is a .
  • priority encoder
  • decoder
  • multiplexer
  • demultiple xer
Answer: priority encoder
Q16 | The prefix on IC's indicates a broader operating temperature range, and the devices are generally used by the military.
  • 54
  • 2n
  • 74
  • ttl
Answer: 54
Q17 | When an open occurs on the input of a TTL device, the output will .
  • go low, because there is no current in an open circuit
  • react as if the open input were a high
  • go high,since full voltage appears across an open
  • still be good, if only the good inputs are used
Answer: react as if the open input were a high
Q18 | The largest truth table that can be implemented directly with an 8-line- to-1-line MUX has .
  • 3 rows
  • 4 rows
  • 8 rows
  • 16 rows
Answer: 8 rows
Q19 | Parity generation and checking is used to detect .
  • which of two numbers is greater
  • errors in binary data transmission
  • errors in arithmetic in computers
  • when a binary counter counts incorrectly
Answer: errors in binary data transmission
Q20 | Except for , STD_LOGIC may have the following values.
  • \z\
  • \u\
  • \?\
  • \l\
Answer: \?\
Q21 | A gate that could be used to compare two logic levels and provide a HIGH output if they are equal is a(n) .
  • xor gate
  • xnor gate
  • nand gate
  • nor gate
Answer: xnor gate
Q22 | VHDL is very strict in the way it allows us to assign and compare                 such as signals, variables, constants, and literals.
  • objects
  • logic_vect ors
  • designs
  • arrays
Answer: objects
Q23 | The AND-OR-INVERT gates are designed to simplify implementation of.
  • pos logic
  • demorgan\s theorem
  • nand logic
  • sop logic
Answer: demorgan\s theorem
Q24 | The output of a gate has an internal short; a current tracer will .
  • identify the defective gate
  • show whether the gate is shorted to v cc or ground
  • probably not be able to locate the problem
  • be able to identify the defective load node
Answer: identify the defective gate
Q25 | Parity generators and checkers use gates.
  • exclusive-and
  • exclusive- or/nor
  • exclusive-or
  • exclusive- nand
Answer: exclusive- or/nor
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