Digital Electronics Set 12
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This set of Digital Electronics Multiple Choice Questions & Answers (MCQs) focuses on Digital Electronics Set 12
Q1 | A 74HC195 4-bit parallel access shift register can be used for
- serial in/serial out operation
- serial in/parallel out operation
- parallel in/serial out operation
- all of the mentioned
Q2 | What is the function of a buffer circuit?
- to provide an output that is inverted from that on the input
- to provide an output that is equal to its input
- to clean up the input
- to clean up the output
Q3 | What is the preset condition for a ring shift counter?
- all ffs set to 1
- all ffs cleared to 0
- a single 0, the rest 1
- a single 1, the rest 0
Q4 | Another way to connect devices to a shared data bus is to use a
- circulating gate
- transceiver
- bidirectional encoder
- strobed latch
Q5 | The full form of SIPO is
- serial-in parallel-out
- parallel-in serial-out
- serial-in serial-out
- serial-in peripheral-out
Q6 | A shift register that will accept a parallel input or a bidirectional serial load and internal shift features is called as?
- tristate
- end around
- universal
- conversion
Q7 | How can parallel data be taken out of a shift register simultaneously?
- use the q output of the first ff
- use the q output of the last ff
- tie all of the q outputs together
- use the q output of each ff
Q8 | What is meant by parallel load of a shift register?
- all ffs are preset with data
- each ff is loaded with data, one at a time
- parallel shifting of data
- all ffs are set with data
Q9 | The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains
- 01110
- 00001
- 00101
- 00110
Q10 | Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first)
- 1100
- 0011
- 0000
- 1111
Q11 | A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains
- 0000
- 1111
- 0111
- 1000
Q12 | With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in
- 4 μs
- 40 μs
- 400 μs
- 40 ms
Q13 | An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of
- 16 us
- 8 us
- 4 us
- 2 us
Q14 | A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?
- ring shift
- clock
- johnson
- binary
Q15 | A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing
- 1101
- 0111
- 0001
- 1110
Q16 | How many clock pulses will be required to completely load serially a 5-bit shift register?
- 2
- 3
- 4
- 5
Q17 | How is an strobe signal used when serially loading a shift register?
- to turn the register on and off
- to control the number of clocks
- to determine which output qs are used
- to determine the ffs that will be used
Q18 | An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time delay between the serial input and the Q3 output?
- 1.67 s
- 26.67 s
- 26.7 ms
- 267 ms
Q19 | What are the three output conditions of a three-state buffer?
- high, low, float
- high-z, 0, float
- negative, positive, 0
- 1, low-z, float
Q20 | The primary purpose of a three-state buffer is usually
- to provide isolation between the input device and the data bus
- to provide the sink or source current required by any device connected to its output without loading down the output device
- temporary data storage
- to control data flow
Q21 | What is the difference between a ring shift counter and a Johnson shift counter?
- there is no difference
- a ring is faster
- the feedback is reversed
- the johnson is faster
Q22 | A latch is an example of a
- monostable multivibrator
- astable multivibrator
- bistable multivibrator
- 555 timer
Q23 | Latch is a device with
- one stable state
- two stable state
- three stable state
- infinite stable states
Q24 | Why latches are called a memory devices?
- it has capability to stare 8 bits of data
- it has internal memory of 4 bit
- it can store one bit of data
- it can store infinite amount of data
Q25 | Two stable states of latches are
- astable & monostable
- low input & high output
- high output & low output
- low output & high input